stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 32

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
III.5.4 - SRAM interface
The SRAM space achieves 1 Mbyte max. It is
always organized in 16 bits. The structure of the
memory plane is shown in the following figures.
Because of the different chips usable, 19 address
wires and 8 NCE (Chip Enable) are necessary to
address the 1 Mbyte. The NCE selects the Most or
Least Significant Byte versus the value of A0 deliv-
ered by the P and the location of chip in the
memory space.
III.5.4.1 - 18K x n SRAM
The Address bits delivered by the Multi-HDLC for
128K x n SRAM circuits are :
ADM0/14 and ADM15/16 (17 bits) corresponding
with A1/17 delivered by the P.
Figure 18 : 128K x 8 SRAM Circuit Memory
III.5.4.2 - 512K x n SRAM
The Address bits delivered by the Multi-HDLC for
512K x n SRAM circuits are :
ADM0/14 and ADM15/18 (19 bits) corresponding
with A1/19 delivered by the P.
32/83
NCE 7
NCE 5
NCE 3
NCE 1
Signals
NCE7
NCE6
NCE5
NCE4
NCE3
NCE2
NCE1
NCE0
Signals
NCE1
NCE0
7
5
3
1
Organization
DM8/15
A19
1
1
1
1
0
0
0
0
128K x 16
NCE 6
NCE 4
NCE 2
NCE 0
A18
1
1
0
0
1
1
0
0
A0 or equiv.
6
4
2
0
A0 or equiv.
DM0/7
1
0
1
0
1
0
1
0
1
0
128K x 8
Figure 19 : 512K x 8 SRAM Circuit Memory
III.5.5 - DRAM Interface
In DRAM, the memory space can achieve up to 16
megabytes organized by 16 bits. Eleven address
wires, four NRAS and two NCAS are needed to
select any byte in the memory. One NRAS signal
selects 1 bank of 4 and the NCAS signals select the
bytes concerned by the transfer (1 or 2 selecting a
byte or a word). The DRAM memory interface is
then defined. The ”RAS only” refresh cycles will
refresh all memory locations. The refresh is pro-
grammable. The frequency of the refresh is fixed
by the memory requirements.
III.5.5.1 - 256K x n DRAM Signals
The Address bits delivered by the Multi-HDLC for
256K x n DRAM circuits are :
ADM0/8 (2 x 9 = 18 bits) corresponding with A1/18
delivered by the P.
Figure 20 : 256K x 16 DRAM Circuit Organization
NCE1
Signals
NRAS3
NRAS2
NRAS1
NRAS0
NCAS1
NCAS0
RAS 3
RAS 2
RAS 1
RAS 0
ADM0/8, NWE, NOE a re conne cte d to e a ch circuit.
1
Organization
DM8/15
CAS1
7
5
3
1
A20
1
1
0
0
DM8/15
512K x 16
NCE0
A19
CAS0
1
0
1
0
6
4
2
0
DM0/7
0
256K x 16
A0 or equiv.
DM0/7
1
0
512K x 8