stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 64

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.14 - HDLC Receive Command Register - HRCR (1A)H
READ : READ COMMAND MEMORY
CH0/4 : These five bits define one of 32 channels.
C1/C0 : COMMAND
P0/1
CRC
AR10 : Address Recognition10
AR11 : Address Recognition 11
AR20 : Address Recognition 20
64/83
bit15
CH4
CH3
: PROTOCOL BITS
: CRC stored in external memory
READ = 1, READ COMMAND MEMORY.
READ = 0, WRITE COMMAND MEMORY.
CRC = 1, the CRC is stored at the end of the frame in external memory.
CRC = 0, the CRC is not stored into external memory.
AR10 = 1, First byte after opening flag of received frame is compared to AF0/7 bits of AFRDR.
If the first byte received and AF0/7 bits are not identical the frame is ignored.
AR10 = 0, First byte after opening flag of receivedframe is not compared to AF0/7 bits of AFRDR
Register.
AR11 = 1, First byte after opening flag of received frame is compared to all ”1”s.If the first byte
received is not all ”1”s the frame is ignored.
AR11 = 0, First byte after opening flag of received frame is not compared to all ”1”s.
AR20 = 1, Secondbyte after opening flag of receivedframe is comparedto AF8/15bits of AFRDR
Register. If the second byte received and AF8/15 bits are not identical the frame is ignored.
AR20 = 0, Second byte after opening flag of received frame is not compared to AF8/15 bits of
AFRDR Register.
C1
P1
0
0
1
1
0
0
1
1
CH2
C0
P0
0
1
0
1
0
1
0
1
CH1
ABORT ; if this command occurs during receiving a current frame, HDLC Controller stops the
reception, generates an interrupt and waits new command such as START orn CONTINUE.
If this command occurs after receiving a frame, HDLC Controller generates an interrupt and waits
a new command such as START or CONTINUE.
START ; Rx DMA Controller is now going to transfer first frame into buffer related to the initial
descriptor. The initial descriptor address is provided by the Initiate Block located in external
memory.
CONTINUE ; Rx DMA Controller is now going to transfer next frame into buffer related to next
descriptor. The next descriptor address is provided by the previous descriptor from which the
related frame had been already received.
HALT ; after receiving frame, HDLC Controller stops the reception, generates an interrupt and
waits a new command such as START or CONTINUE.
HDLC
Transparent Mode 1 (per byte) ; the fill character defined in FCR Register is taken into account.
Transparent Mode 2 (per byte) ; the fill character defined in FCR Register is not taken into account.
Reserved
CH0
READ
AR21
After reset (0000)
AR20
bit8
Transmission Mode
AR11
Commands Bits
bit7
H
AR10
CRC
Nu
P1
P0
C1
bit 0
C0