stlc5464 STMicroelectronics, stlc5464 Datasheet
stlc5464
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stlc5464 Summary of contents
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... IN . MEMORY PQFP160 PACKAGE May 1997 DESCRIPTION The STLC5464 is a Subscriber line interface card controller for Central Office, Central Exchange, NT2 and PBX capable of handling : - 16 U Interfaces Megabits line interface cards SLICs (Plain Old Telephone Service Mixed analogue and digital Interfaces (SLICs or ...
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... STLC5464 CONTENTS I PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.1 PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3 PIN DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.1 Input Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I.3.2 Output Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... STATIC MEMORIEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VII MICROPROCESSOR TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VII.1 ST9 FAMILY MOD0=1, MOD1=0, MOD2 VII.2 80C188 MOD0=1, MOD1=1, MOD2 VII.3 80C186 MOD0=1, MOD1=1, MOD2 VII.4 68000 MOD0=0, MOD1=0, MOD2 VII.5 TOKEN RING TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VII.6 MASTER CLOCK TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STLC5464 Page ...
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... STLC5464 CONTENTS (continued) VIII INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIII.1 IDENTIFICATION AND DYNAMIC COMMAND REGISTER . . . . . . . . . . . IDCR (00)H VIII.2 GENERAL CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GCR (02)H VIII.3 INPUT MULTIPLEX CONFIGURATION REGISTER IMCR0 (04)H VIII.4 INPUT MULTIPLEX CONFIGURATION REGISTER IMCR1 (06)H VIII.5 OUTPUT MULTIPLEX CONFIGURATION REGISTER OMCR0 (08)H VIII.6 OUTPUT MULTIPLEX CONFIGURATION REGISTER OMCR1 (0A)H VIII ...
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... RECEIVE COMMAND / INDICATE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IX.5.1 Receive Command / Indicate Interrupt when TSV = IX.5.2 Receive Command / Indicate Interrupt when TSV = IX.6 RECEIVE MONITOR INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IX.6.1 Receive Monitor Interrupt when TSV = IX.6.2 Receive Monitor Interrupt when TSV = PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STLC5464 Page ...
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... STLC5464 LIST OF FIGURES I PIN INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 1 : General Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . III FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2 : Switching Matrix Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3 : Unidirectional and Bidirectional Connections . . . . . . . . . . . . . . . . . . . . . . Figure 4 : Loop Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Figure 38 : 80C188 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 39 : 80C186 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 40 : 80C186 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 41 : 68000 Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 42 : 68000 Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 43 : Token Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 44 : Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIII INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IX EXTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STLC5464 Page ...
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... STLC5464 I - PIN INFORMATION I.1 - Pin Connections 1 NRESET 2 XTAL1 3 XTAL2 4 WDO VCXO IN 8 VCXO OUT 9 DCLK 10 CLOCKA 11 CLOCKB 12 FRAMEA 13 FRAMEB FSCG 18 FSCV 19 PSS 20 DIN0 21 DIN1 22 DIN2 23 DIN3 24 DIN4 25 DIN5 26 DIN6 27 DIN7 28 DIN8 DOUT0 32 DOUT1 ...
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... O8D = Output CMOS 8mA, Open Drain ; O8T = Output CMOS 8mA, Tristate Function = 32000kHz can be applied to this input (or one pin Min < f < +50. Hysteresis ; Pull- Output CMOS 8mA, ”1” and ”0” at Low Impedance ; O8DT = Output CMOS 8mA, Open Drain or Tristate ; STLC5464 9/83 ...
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... STLC5464 I - PIN INFORMATION (continued) I.2 - Pin Description (continued) Pin N Symbol Type TIME DIVISION MULTIPLEXES (TDM) 20 DIN0 I1 TDM0 Data Input 0 21 DIN1 I1 TDM1 Data Input 1 22 DIN2 I1 TDM2 Data Input 2 23 DIN3 I1 TDM3 Data Input 3 24 DIN4 I1 TDM4 Data Input 4 25 DIN5 I1 TDM5 Data Input 5 ...
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... Pull- Output CMOS 4mA ; O4T = O4 + Tristate ; O8D = Output CMOS 8mA, Open Drain ; O8T = Output CMOS 8mA, Tristate Function Hysteresis ; Pull- Output CMOS 8mA, ”1” and ”0” at Low Impedance ; O8DT = Output CMOS 8mA, Open Drain or Tristate ; STLC5464 11/83 ...
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... STLC5464 I - PIN INFORMATION (continued) I.2 - Pin Description (continued) Pin N Symbol Type MICROPROCESSOR INTERFACE (continued) 100 D9 I/O Data bit 9 for P if not multiplexed 101 D10 I/O Data bit 10 for P if not multiplexed 102 D11 I/O Data bit 11 for P if not multiplexed 103 D12 I/O Data bit 12 for P if not multiplexed ...
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... I.3.3 - Input/Output Pin Definition I/O : Input TTL/ Output CMOS 8mA. N.B. XTAL1 : this input is CMOS. XTAL2 : NTEST pin at 0 has no effect on this pin. Function Hysteresis ; Pull- Output CMOS 8mA, ”1” and ”0” at Low Impedance ; O8DT = Output CMOS 8mA, Open Drain or Tristate ; STLC5464 13/83 ...
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... The clock selection and time synchronization function, - The interrupt controller, - The watchdog GCI1 V10 CLOCK SELECTION 18 FSCV* 17 FSCG To 9 DCLK Internal 16 FS Circuit C/I MON C/I MON 49 INT0 INTERRUPT CONTROLLER 50 INT1 RAM RAM INTERFACE Bus STLC5464 ...
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... Any time slot of an Output TDM can be internally looped back on the time slot which has the same TDM number and the same TS number (OTDMi, TSj) ----> (ITDMi, TSj). In the case of a bidirectional connection, only the one specified by the microprocessor is concerned by the loop back (see Figure 4 on Page 17). STLC5464 15/83 ...
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... STLC5464 III - FUNCTIONAL DESCRIPTION (continued) Figure 2 : Switching Matrix Data Path DIN 0/7 BIT SYNCHRO D7 DIN’ 0/7 D4/5 Tx HDLC HDLCM 1 LOOP DATA IMTD A MEMORIES 64kb/s and Sequence n x 64kb/s Integrity CM INS D4/5 Tx GCI D7 GCIR 1 D0/7 BIT SYNCHRO DOUT 0/7 16/83 PRSG : Pseudo Random Sequence Generator ...
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... Figure 6 on Page 19). In this case, the delay is definedby a singleexpres- sion : Constant Delay = (32 - ITSx OTSy So, the delay in sequence integrity mode varies from time slots. STLC5464 ITSx,ITDMp DOWN STREAM OTSx, OTDMp ...
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... STLC5464 III - FUNCTIONAL DESCRIPTION (continued) Figure 5 : Variable Delay through the matrix with ITDM = OTS y > ITS the n Va ria ble OTS y - ITSx Time ITS0 ITS x ITS x+1 ITSx+2 Inpu t Fra > OTS 0 ...
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... Case : If OTSy < ITSx, then Variable Delay (ITSx - OTSy) TimeSlots Frame n ITS0 ITSx Input Frame y < x OTS0 Output Frame OTSy Variable Delay : 32 - (ITSx - OTSy) TimeSlots Frame ITS31 ITS0 Frame ITS31 ITS0 ITSx OTSy 32 TimeSlots Frame ITS31 ITS0 OTSy 32 TimeSlots STLC5464 ITS31 OTS31 ITS31 OTS31 ITSx ITS31 OTS31 19/83 ...
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... STLC5464 III - FUNCTIONAL DESCRIPTION (continued) Figure 7 : Constant Delay through the matrix with Delay = (32 -ITSx OTS y ITS : OTS : Frame n ITS0 ITS31 ITS0 Min. Constant Delay = 33TS 1 + Max. Constant Delay = 95 Time Slots (32 - ITSx) 20/83 Input Time S lot Output TimeS lot ...
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... Data (optional) Data (last byte) FCS (first byte) FCS (second byte) Closing Flag - Opening Flag - One or two bytes for address recognition (recep- tion) and insertion (transmission) - Data bytes with bit stuffing - Frame Check Sequence: CRC with polynomial G(x) = x16 +x12+x5+1 - Closing Flag. STLC5464 21/83 ...
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... STLC5464 III - FUNCTIONAL DESCRIPTION (continued) Figure 8 : HDLC and DMA Controller Block Diagram F rom Output 7 of the Matrix DIN 8 Dire ct HDLC Input 32 Rx HDLC 32 ADDRE S S RECOGNITION 32 Rx FIFO ’ DMAC P INTERFACE 22/83 DOUT 6 Direct HDLC O utput From Output 6 of the Matrix ...
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... In case of a collision, the frame which has been aborted is automatically retransmitted by the DMA controller without warning the microprocessor of this collision. The frame can be located in several buffers in external memory. The collision can be detected from the second bit of the opening frame to the last but one bit of the closing frame. STLC5464 23/83 ...
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... STLC5464 III - FUNCTIONAL DESCRIPTION (continued) III.2.3 - Time Slot Assigner Memory Each HDLC channel is bidirectional and configu- rate by the Time Slot Assigner (TSA). The TSAis a memoryof 32 words (one per physical Time Slot) where all of the 32 input and output time slots of the HDLC controllers can be associated to logical HDLC channels ...
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... CONTROLLER 31 RDA Receive Descriptor 2 NRDA RBA Receive Receive Buffer 1 Buffer 2 Receive Descriptor 3 NRDA RBA Receive Buffer 3 Initialization Block channels TRANSMIT 0 TDA DMA 1 TDA CONTROLLER 31 TDA Transmit Descriptor 2 NTDA TBA Transmit Transmit Buffer 1 Buffer 2 Transmit Descriptor 3 NTDA TBA Transmit Buffer 3 STLC5464 25/83 ...
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... STLC5464 III - FUNCTIONAL DESCRIPTION (continued) III.2.5 - Transparent Modes In the transparentmode, the Multi-HDLC transmits data in a completely transparent manner without performing any bit manipulation or Flag insertion. The transparent mode is per byte function. Two transparent modes are offered : - First mode : for the receive channels, the ...
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... The reception of C/I and Monitor messages are managed by two interrupt queues. In transmission, a transmit command register is implemented for each C/I and monitor channel (16 C/I transmit command registers and 16 Monitor transmit command registers). Those registers are accessible in read and write modes by the micro- processor. STLC5464 CGI Channel 7 TS29 TS30 TS31 B2 MON S/C ...
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... STLC5464 III - FUNCTIONAL DESCRIPTION (continued) Figure C/I and Monitor Channel Path DIN 5 DIN 4 GCI1 GCI0 D Channels from Tx HDLC III.4 - Microprocessor Interface III.4.1 - Description The Multi-HDLC circuit can be controlledby severa types of microprocessors (ST9, Intel/Motorola data bits interfaces) such ST9 family - INTEL 80C188 8 bits ...
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... BUS ARBITRATION INT0/1 WDO NRES ET CS 0/1 ARDY P NWR INTERFACE NR D ALE A8/19 AD0/7 INT0/1 WDO NRES ET CS 0/1 NBHE ARDY P NWR INTERFACE NR D ALE A16/19 AD0/15 STLC5464 STATIC or DYNAMIC RAM (organize bits ) Data Bus STATIC or DYNAMIC RAM (organized by 16 bits) Data Bus 29/83 ...
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... STLC5464 III - FUNCTIONAL DESCRIPTION (continued) Figure 16 : Microprocessor Interface for MOTOROLA 68000 MOTOROLA 68000 Figure 17 : Microprocessor Interface for ST9 ST9 30/83 INT0/1 WDO NRES ET CS 0/1 NDTACK R/NW P NUDS INTERFACE NLDS NAS A1/23 AD0/15 INT0/1 WDO NRE 0/1 WAIT P R/NW INTERFACE NDS NAS A8/15 AD0/7 ...
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... Each cycle is equal 1/f with f the frequencyof signal applied to the Crystal 1 input and p selected by the user. Shared memory size required by the application 0 2(256Kx16) 4(256Kx16) 4(1Mx4) 8(1Mx4) 1(1Mx16) 2(1Mx16) Not possible 8(128Kx8) 2(512kx8) STLC5464 16(1Mx4) 4(1Mx16) 4(4Mx4) 8(4Mx4) 1(4Mx16) 2(4Mx16) 31/83 ...
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... STLC5464 III - FUNCTIONAL DESCRIPTION (continued) III.5.4 - SRAM interface Signals A19 A18 NCE7 1 1 NCE6 1 1 NCE5 1 0 NCE4 1 0 NCE3 0 1 NCE2 0 1 NCE1 0 0 NCE0 0 0 The SRAM space achieves 1 Mbyte max always organized in 16 bits. The structure of the memory plane is shown in the following figures ...
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... The TRI, TRO signals are managed by the bus arbitration function too. When a chip has finished its tasks, it sends a pulse the next chip. Figure 23 : Chain of n Multi-HDLC Components Bus STLC5464 NCAS DM8/15 DM0/7 ...
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... STLC5464 III - FUNCTIONAL DESCRIPTION (continued) III.7 - Clock Selection and Time Synchronization III.7.1 - Clock Distribution Selection and Supervision Two clock distributions are available : Clock at 4.096MHzor 8.192MHz and a synchronizationsig- nal at 8kHz. The component has to select one of these two distributions and to check its integrity (see Figure 25 and Paragraph ” ...
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... For debugging function, each interrupt word of the CI interruptqueue and monitor interrupt queue can be followed by a timestamped word composed of a counter which runs in the range of 250 s. The counter is the same as the watchdog counter. Consequently,the watchdogfunctionisn’t available at the same time. STLC5464 ” on Page 74). H 35/83 ...
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... STLC5464 III - FUNCTIONAL DESCRIPTION (continued) Figure 26 : The Three Circular Interrupt Memories IBA IBA + 256 INITIALIZATION BLOC K IBA + 254 III.9 - Watchdog This function is used to control the activity of the application composed of a counter which counts down from an initial value loaded in the Timer register by the microprocessor. ...
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... Parameter Test Conditions Test Conditions Test Conditions 1MHz @ 0V Test Conditions (see Note (see Note Test Conditions C = 100pF 1.5k STLC5464 Value Unit -0.5, 6.5 V -0. 0 -55, +125 C Min. Typ. Max. Unit 400 mW Min. Typ. Max. Unit 4.75 5. ...
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... STLC5464 V - CLOCK TIMING V.1 - Synchronization Signals delivered by the system For one of three different input synchronizations which is programmed, FSCG and FSCV* signals delivered by the Multi-HDLC are in accordance with the figure hereafter. Figure 27 : Clocks received and delivered by the Multi-HDLC CLOCK B t2 CLOCK Mode ...
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... Set-up Echo/DCLK (rising edge) t9 Hold Time Echo/DCLK (rising edge Bit 7, Time S lot 31 Bit 0, Time Slot Min. Id CLOCKA 244 20 20 205 STLC5464 t7 Typ. Max. Unit 244 Id CLOCKA 488 t1- 125000-244 100 ns ...
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... STLC5464 V - CLOCK TIMING (continued) V.3 - GCI Interface Figure 29 : GCI Synchro Signal delivered by the Multi-HDLC ived by the Multi-HDLC CH0 DIN4/5 DOUT4/5 GCI DCLK de livered by the Multi-HDLC livered by the Multi-HDLC DOUT0/ FSCG is connected to FS DIN0/8 The four Multiplex Configura tion Registers (no de lay betwee n FS and Multiplexes ). ...
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... Clock Period 4096kHz t3 DCLK to FSCV* t5 Duration FSCV* t6 Clock to Data 50pF Clock to Data 100pF t7 Set-up Time Data/DCLK t7 Hold Time Data/DCLK 125 s CH1 Bit 3, Time S lot Parameter STLC5464 CH7 MON D C/I AT Min. Typ. Max. Unit 244 244 100 ...
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... STLC5464 VI - MEMORY TIMING VI.1 - Dynamic Memories Figure 31 : Dynamic Memory Read Signals from the Multi-HDLC NDS fro (or e quivalent) a MASTERCLOCK a pplied to XTAL1 P in NRAS 0/3 HZ NCAS 0/1 NWE ADM0/10 NOE DM0/15 from DRAM Circuit HZ Note : MBL De finition Symbol T Delay between Data Strobe from the mP and beginning of cycle ...
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... Td Data Valid after beginning of cycle (30 pF) Note : Total Cycle : Tota l Write Cycle Tv ignal from the MHDLC is high impe dance outside this time if MBL = 0 Parameter STLC5464 1 Min. Typ. Max. Unit 32 33 MHz 1/f 2/f ns 1/f 2/f ns ...
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... STLC5464 VI - MEMORY TIMING (continued) VI.2 - Static Memories Figure 33 : Static Memory Read Signals from the Multi-HDLC NDS fro (or equivalent) a MASTERCLOCK applied to XTAL1 ADM0/18 NCE0/7 NWE NOE HZ DM0/15 from S RAM Circuit Note : MBL De finition Symbol T Delay between Data Strobe delivered by the mP and beginning of ...
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... Delay between Masterclock and Edge of each signal delivered by the MHDLC (30pF) Tuv NCE width Note : Total Write Cycle : Tuv + 1/f Total Write Cycle Tuv Each signal delivered by the MHDLC is high impedance outside this time Parameter STLC5464 1 Min. Typ. Max. Unit 2 1/f ...
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... STLC5464 VII - MICROPROCESSOR TIMING VII.1 - ST9 Family MOD0=1, MOD1=0, MOD2=0 Figure 35 : ST9 Read Cycle NCS0/1 READY t4 NAS/ ALE NDS/ NRD t5 AD0/7 R/W / NWR Symbol t1 Delay Ready / Chip Select (if t3 > t1), (30pF) t2 Hold Time Chip Select /Data Strobe t3 Delay Ready / NAS (if t1 > t3), (30pF) ...
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... Hold Time Data / Data Strobe t9 Set-up Time R/W / NAS t10 Hold Time R/W / Data Strobe t11 Width NDS when immediate access t12 Delay NDS / NCS t1 t3 t12 t11 t7 t6 D0/7 A0/7 t9 t10 Parameter STLC5464 t2 t8 Min. Typ. Max. Unit ...
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... STLC5464 VII - MICROPROCESSOR TIMING (continued) VII.2 - 80C188 MOD0=1, MOD1=1, MOD2=0 Figure 37 : 80C188 Read Cycle NCS0/1 READY NAS /ALE t4 NDS /NRD t5 AD0/7 R/W / NWR Symbol t1 Delay Ready / Chip Select (if t3 > t1), (30pF) t2 Hold Time Chip Select / NRD t3 Delay Ready / ALE (if t1 > t3), (30pF) ...
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... Delay Ready / ALE (if t1 > t3), (30pF) t4 Width ALE t5 Set-up Time Address / ALE t6 Hold Time Address / ALE t7 Set-up Time Data / NWR t8 Hold Time Data / NWR t12 Delay NWR / NCS t1 t3 t12 t6 D0/7 A0/7 t7 Parameter STLC5464 t2 t8 Min. Typ. Max. Unit ...
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... STLC5464 VII - MICROPROCESSOR TIMING (continued) VII.3 - 80C186 MOD0=1, MOD1=1, MOD2=1 Figure 39 : 80C186 Read Cycle NCS0/1 READY t4 NAS /ALE NDS /NRD t5 AD0/15 R/W / NWR t9 NBHE A16/19 Symbol t1 Delay Ready / Chip Select (if t3 > t1), (30pF) t2 Hold Time Chip Select / NRD t3 Delay Ready / ALE (if t1 > t3), (30pF) ...
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... Hold Time Data / NWR t9 Set-up Time NBHE-Address A16/19 / ALE t10 Hold Time Address 16/19 / ALE t11 Hold Time NBHE- / NWR t12 Delay NWR / NCS t1 t3 t12 t6 D0/15 A0/15 t7 t10 NBHE NBHE A16/19 Parameter STLC5464 t2 t8 t11 Min. Typ. Max. Unit ...
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... STLC5464 VII - MICROPROCESSOR TIMING (continued) VII.4 - 68000 MOD0=0, MOD1=0, MOD2=1 Figure 41 : 68000 Read Cycle NCS0/1 NDTACK NAS/ ALE SIZE0 /NLDS SIZE1 /NUDS A1/23 R/W / NWR D0/15 Symbol t1 Delay NDTACK / NCS0/1 (if t3 > t1), (30pF) Delay when immediate access t2 Hold Time Chip Select / NLDS-NUDS t3 Delay NDTACK / NLDS-NUDS Falling Edge (if t1> t3), (30pF) ...
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... Delay NDTACK / NLDS-NUDS Rising Edge t5 Set-up Time Address / NAS t6 Hold Time Address / NLDS-NUDS t9 Set-up Time Data / NLDS-NUDS t10 Hold Time Data / NLDS-NUDS t12 Delay NDS / NCS t1 t3 t12 t5 A1/23 t9 Parameter STLC5464 t10 Min. Typ. Max. Unit ...
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... STLC5464 VII - MICROPROCESSOR TIMING (continued) VII.5 - Token Ring Timing Figure 43 : Token Ring MASTER CLOCK (applied to XTAL1 P in) TRO TRI Symbol 1 Masterclock frequency a Delay between Masterclock Rising Edge and Edges of TRO Pulse delivered by the MHDLC (10pF) t Set-up Time TRI/Masterclock Masterclock Falling Edge ...
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... TRD = 0, the token ring is authorized ; when the token will be launched,it will appearon TRO pin. bit8 bit7 bit8 bit7 bit8 bit7 HCL SYN1 SYN0 D7 EVM After reset (0000) H STLC5464 bit bit 0 Nu RSS WDR TL bit 0 TSV TRD PMA WDD 55/83 ...
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... STLC5464 VIII - INTERNAL REGISTERS (continued) TSV : Time Stamping Validated TSV = 1, the time stamping counter becomes a free binary counter and counts down from 65535 step of 250ms (Total = 16384ms event occurs when the counter indicates A and if the next event occurs when the counter indicates B then : t = (A-B) x 250ms is the time which haspassedbetweenthe two eventswhich have beenstored in memoryby the InterruptController (for Rx C/I and Rx MON CHANNEL only) ...
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... See definition in next Paragraph. bit8 bit7 After reset (0000) H bit8 bit7 After reset (0000 7), delayed or not. i 7), delayed or not. i 7). STEP for each Input Multiplex 0/7 delayed or not taken into account. bit8 bit7 After reset (0000) H STLC5464 bit 0 bit 0 bit 0 57/83 ...
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... STLC5464 VIII - INTERNAL REGISTERS (continued) VIII.6 - Output Multiplex Configuration Register 1 - OMCR1 (0A)H bit15 OMV7 DEL7 ST(7)1 ST(7)0 OMV6 DEL6 ST(6)1 ST(6)0 OMV5 DEL5 ST(5)1 ST(5)0 OMV4 DEL4 ST(4)1 ST(4)0 ST(i)0 : STEP0 for each Output Multiplex i(0 ST(i)1 : STEP1 for each Output Multiplex i(0 DEL(i); : DELAYED Multiplex i(0 DEL ( Each bit is transmitted on the rising edge of the double clock without delay. ...
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... For OTSy and OTDMq with PSS pin is at ”1” during the first bit of the frame defined by the Frame synchronization Signal (FS PSS Pin is at ”0” during the bit time defined by OTSy and OTDMq. SOURCE REGISTER (SRCR) bit8 bit7 SI IM2 IM1 IM0 ITS 4 ITS 3 ITS 2 ITS 1 ITS 0 After reset (0000 31; STLC5464 bit 0 59/83 ...
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... STLC5464 VIII - INTERNAL REGISTERS (continued) VIII.9 - Connection Memory Address Register - CMAR (10)H ACCESS MODE REGISTER (AMR) bit15 CACL CAC Nu This 16 bit register is constitutedby two registers : DESTINATIONREGISTER (DSTR) and ACCESSMODE REGISTER (AMR) respectively 8 bits and 6 bits. Remark : It is mandatory for this specific register to write successively : ...
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... After software reset (bit 2 of IDCR Register) or pin reset the automate above-mentioned is working. The automate is stopped when the microprocessor writes TAAR Register with HDI = 0. bit8 bit7 After reset (0000 stays at its maximum value. H bit8 bit7 Nu HDI After reset (0100) H STLC5464 bit bit 61/83 ...
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... STLC5464 VIII - INTERNAL REGISTERS (continued) VIII.12 - Time Slot Assigner Data Register - TADR (16)H bit15 V11 V10 CH0/4 : CHANNEL0/4 These five bits define one of 32 channels associated to TIME SLOT defined by the previous Register (TAAR). V1/8 : VALIDATION The logical channel CHx is constituted by each subchannel and validated by V1/8 bit ...
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... CF : Common flag the closing flag of previous frame and opening flag of next frame are identical if the next frame is ready to be transmitted the closing flag of previous frame and opening flag of next frame are distinct. Commands Bits Transmission Mode STLC5464 63/83 ...
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... STLC5464 VIII - INTERNAL REGISTERS (continued) VIII.14 - HDLC Receive Command Register - HRCR (1A)H bit15 CH4 CH3 CH2 CH1 CH0 READ READ : READ COMMAND MEMORY READ = 1, READ COMMAND MEMORY. READ = 0, WRITE COMMAND MEMORY. CH0/4 : These five bits define one of 32 channels. C1/C0 : COMMAND ABORT ; if this command occurs during receiving a current frame, HDLC Controller stops the reception, generates an interrupt and waits new command such as START orn CONTINUE ...
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... The value of the first received byte must be equal either to that of AF0 ”1” and the value of the second received byte must be equal either to that of AF8/ all ”1”s. bit8 bit7 After reset (0000) H STLC5464 bit 65/83 ...
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... STLC5464 VIII - INTERNAL REGISTERS (continued) VIII.16 - Address Field Recognition Data Register - AFRDR (1E)H bit15 AF15 AF14 AF13 AF12 AF11 AF10 AF0/15 : ADDRESS FIELD BITS AF0/7 ; First byte received; AF8/15: Second byte received. These two bytes are stored into Address Field Recognition Memory when AFRAR is written by the microprocessor ...
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... For definition see GCI Channels Definition Register above. bit8 bit7 TDM4 TDM5 GCI CHANNEL 2 After reset (0000) H bit8 bit7 TDM4 TDM5 GCI CHANNEL 4 After reset (0000) H bit8 bit7 TDM4 TDM5 GCI CHANNEL 6 After reset (0000) H STLC5464 bit 0 TDM4 bit 0 TDM4 bit 0 TDM4 67/83 ...
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... STLC5464 VIII - INTERNAL REGISTERS (continued) VIII.22 - Transmit Command / Indicate Register - TCIR (2A)H bit15 0 G0 CA2 CA1 CA0 READ When this register is written by the microprocessor, these different bits mean : READ : READ C/I MEMORY READ = 1, READ C/I MEMORY. READ = 0, WRITE C/I MEMORY. CA 0/2 : TRANSMIT COMMAND/INDICATE MEMORY ADDRESS CA 0/2 : These bits define one of eight Command/Indicate Channels. ...
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... Time Out one millisecond the remote receiver has not acknowledged the byte which has been transmitted one millisecond ago. bit8 bit7 TIV FABT After reset (000F) H bit8 bit7 ABT STLC5464 bit 0 L NOB 0 Nu bit 0 L NOBT EXE IDLE 69/83 ...
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... STLC5464 VIII - INTERNAL REGISTERS (continued) VIII.24 - Transmit Monitor Data Register - TMDR (2E)H bit15 M18 M17 M16 M15 M14 M13 M08/01 : First Monitor Byte to transmit. M08 bit is transmitted first. M18/11 : Second Monitor Byte to transmit if NOB = 0 (bit of TMAR). M18 bit is transmitted first. VIII.25 - Transmit Monitor Interrupt Register - TMIR (30)H ...
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... Entity definition : DMA Controller 0 1 Microprocessor DMA Controller 1 1 Interrupt Controller bit8 bit7 After reset (E400) H Entity STLC5464 Tuv 30ns 60ns 90ns 120ns Twz 30ns 60ns 90ns 120ns bit REF 71/83 ...
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... STLC5464 VIII - INTERNAL REGISTERS (continued) PRIORITY 5 is the last priority for DRAM Refresh if validated. DRAM Refresh obtains PRIORITY 0 (the first priority) automatically when the first half cycle is spend without access to memory. After reset (E400) , the Rx DMA Controller has the PRIORITY 1 H the Microprocessor has the PRIORITY 2 ...
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... PRSR = 1,the Pseudo Random Sequencetransmitted by the generatorhas been recovered by the analyzer. SFCO : Sequence Fault Counter Overload SFCO = 1, the Fault Counter has reached the value FFFF(H). bit8 bit7 INT ICOV FWAR FOV FWAR FOV FWAR After reset (0000) H STLC5464 bit 0 MTX MRX C/IRX HDLC . H 73/83 ...
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... STLC5464 VIII - INTERNAL REGISTERS (continued) VIII.30 - Interrupt Mask Register - IMR (3A)H bit15 Nu Nu IM13 IM12 IM11 IM10 IM13/0 : INTERRUPT MASK 0/7 When IM0 = 1, HDLC bit is masked. When IM1 =1, C/IRX bit is masked. When IM2 = 1, MRX bit is masked. When IM3 = 1, MTX bit is masked. When IM4 = 1, ICOV bit is masked When IM5 = 1, RxFWAR bit is masked ...
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... Not used Transmit Descriptor Address (TDA Low) Not used Receive Descriptor Address (RDA Low) Not used Transmit Descriptor Address (TDA Low) Not used Receive Descriptor Address (RDA Low) STLC5464 bit0 TDA High RDA High TDA High RDA High TDA High RDA High ...
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... STLC5464 IX - EXTERNAL REGISTERS (continued) IX.2 - Receive Descriptor This receive descriptor is located in shared memory. The quantity of descriptors is limited by the memory size only RDA+00 IBC EOQ RDA+02 Not used RDA+04 RDA+06 Not used RDA+08 RDA+10 FR ABT OVF FCRC The 5 first words located in shared memory to RDA+00 from RDA+08 are written by the microprocessor and read by the DMAC only ...
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... PRI = 0, if CSMA/CR is validated for this channel the priority class is 10. (see Register CSMA Number of Bytes to be Transmitted (NBT) CRC PRI C Transmit Buffer Address Low (16 bits) Next Transmit Descriptor Address Low (16 bits) STLC5464 TBA High (8 bits) NTDA High (8 bits) 77/83 ...
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... STLC5464 IX - EXTERNAL REGISTERS (continued) IX.3.2 - Bits written by the Rx DMAC only CFT : Frame correctly transmitted CFT = 1, the Frame has been correctly transmitted. CFT = 0, the Frame has not been correctly transmitted. ABT : Frame Transmitting Aborted ABT = 1, the frame has been aborted by the microprocessor during the transmission. ...
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... This location becomes free for the Interrupt Controller GCI 0 corresponding to DIN4 input and DOUT4 output GCI 1 corresponding to DIN5 input and DOUT5 output. A2/0 : COMMAND/INDICATE Channel being owned by GCI 0 or GCI 1 C6/1 : New Primitive received twice consecutively bit8 bit7 STLC5464 bit 79/83 ...
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... STLC5464 IX - EXTERNAL REGISTERS (continued) IX.5.2 - Receive Command / Indicate Interrupt when TSV = 1 Time Stamping validated (bit of GCR Register) bit15 T15 T14 T13 T12 T11 T10 These two words are located in the Command/Indicate interrupt queue ; IQSR Register indicates the size of this interrupt queue located in the external memory. ...
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... M11/18 : Next new Byte received twice consecutively if GCI Protocol has been validated. This byte is at ”1” in case of V* protocol. T15/0 : Binary counter value when a new primitive is occurred. bit8 bit7 A1 A0 M12 M11 STLC5464 bit 0 ODD 81/83 ...
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... STLC5464 X - PACKAGE MECHANICAL DATA 160 PINS - PLASTIC QUAD FLAT PACK Millimeters Dimensions Min. Typ 0.25 A2 3.17 3.42 B 0.22 C 0.13 D 30.95 31.20 D1 27.90 28.00 D3 25.35 e 0.65 E 30.95 31.20 E1 27.90 28.00 E3 25.35 L 0.65 0.80 L1 1.60 K 82/83 Inches Max. Min. Typ. 4.07 0.010 3.67 0.125 0.135 0.38 0.009 0.23 0.005 31.45 1.219 1.228 28.10 1.098 1.102 0.998 0.026 31.45 1.219 1.228 28.10 1.098 1.102 0.998 ...
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... C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S. system, is granted provided that the system conforms to STLC5464 83/83 ...