stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 34

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
III.7 - Clock Selection and Time Synchronization
III.7.1 - Clock Distribution Selection
Two clock distributions are available : Clock at
4.096MHzor 8.192MHz and a synchronizationsig-
nal at 8kHz. The component has to select one of
these two distributions and to check its integrity
(see Figure 25 and Paragraph ”General Configura-
tion Register GCR (02)H” on Page 57).
DCLK, FSCGCI and FSCV* are output on three
external pins of the Multi-HDLC . DCLK is the clock
selected between Clock A and Clock B. FSCGCI
and FSCV* are functions of the selected distribu-
tion and respect the GCI and V* frame synchroni-
zation specifications.
The supervision of the clock distribution consists of
verifying its availability. The detection of the clock
absence is done in less than 250 s. In case the
clock is absent, an interrupt is generated with a
4kHz recurrence. Then the clock distribution is
switched by the microprocessor. This change of
clock occurs on a falling edge of the new selected
distribution.
Figure 24 : MHDLC Clock Generation
34/83
FRAME A
FRAME B
CLOCK A
CLOCK B
and Supervision
S elect A or B
(S ELB)
REF. CLOCK
FRAME A a nd CLOCK A
CLOCK S ELECTION
GENERAL CONFIGURATION REGISTER (GCR)
A or B
S e lecte d
(BS EL)
a re s elected
At RES ET
De a ctivation
S upervision
RES ET
(CS D)
Clock
from 250 s
Clock Lack
De te ction
INT1
HCL
Depending on the applications, three different sig-
nals of synchronization (GCI, V* or Sy) can be
provided to the component. The clock A/B fre-
quency can be a 4096 or 8192kHz clock. The
component is informed of the synchronization and
clocks that are connectedby software.The timings
of the different synchronization are given Page 38.
III.7.2 - VCXO Frequency Synchronization
An external VCXO can be used to provide a clock
to the transmission components. This clock is con-
trolled by the main clock distribution (Clock A or
Clock B at 4096kHz). As the clock of the transmis-
sion component is 15360 or 16384kHz,a configur-
able function is necessary.
The VCXO frequency is divided by P (30 or 32) to
provide a common sub-multiple (512kHz) of the
reference frequency CLOCKA or CLOCKB
(4096kHz). The comparison of these two signals
gives an error signal which commands the VCXO.
Two external pins are needed to perform this func-
tion : VCXO-IN and VCXO-OUT (see Figure 26 on
Page 35).
Fra me
Clock
S YN1
ADAP TATION
CLOCK
S YN0
To the interna l
MHDLC
FS CV*
FS CGCI
DCLK