stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 61

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

VIII - INTERNAL REGISTERS (continued)
TC
VIII.10 - Sequence Fault Counter Register - SFCR (12)H
This register is read only.
When this register is read by the microprocessor, this register is reset (0000)
F0/15 : FAULT0/15
VIII.11 - Time Slot Assigner Address Register - TAAR (14)H
READ : READ MEMORY
TS0/4 : TIME SLOTS0/4
HDI
N.B.
bit15
bit15
TS4
F15
After software reset (bit 2 of IDCR Register) or pin reset the automate above-mentioned is working.
The automate is stopped when the microprocessor writes TAAR Register with HDI = 0.
TS3
: Transparent Connection
: HDLC INIT
F14
TC = 1, if READ = 0 :
CAC = 0 and CACL = 0. The DSTR bits are taken into account instead of SRCR bits. SRCR bits
are ignored (Destination and Source are identical). The contents of Input time slot i - Input
multiplex j is switched into Output time slot i - Output multiplex j.
CAC = 0 and CACL = 1. Up to 32 ”Transparent Connections” are set up.
CAC = 1 and CACL = 0. Up to 256 ”Transparent Connections” are set up.
TC = 0, Write and Read Connection Memory in the normal way.
Number of faults detected by the Pseudo Random Sequence analyzer if the analyzer has been
validated and has recovered the receive sequence.
When the Fault Counter Register reaches (FFFF)
READ = 1, Read Time slot Assigner Memory.
READ = 0, Write Time slot Assigner Memory.
These five bits define one of 32 time slots in which a channel is set-up or not.
HDI = 1, TSA Memory, Tx HDLC, Tx DMA, Rx HDLC, Rx DMA and GCI controllers are reset
within 250ms. An automate writes data from Time slot Assigner Data Register (TADR) (except
CH0/4 bits) into each TSA Memory location. If the microprocessor reads Time slot Assigner
Memory after HDLC INIT, CH0/4 bits of Time slot Assigner Data Register are identical to TS0/4
bits of Time slot Assigner Address Register.
HDI = 0, Normal state.
TS2
F13
TS1
F12
TS0
F11
READ
F10
F9
Nu
After reset (0000)
After reset (0100)
bit8
F8
HDI
bit8
bit7
F7
bit7
r
H
H
H
F6
it stays at its maximum value.
e
F5
s
F4
e
H
.
F3
r
F2
v
STLC5464
F1
e
bit 0
bit 0
61/83
F0
d