stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 62

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5464
VIII - INTERNAL REGISTERS (continued)
VIII.12 - Time Slot Assigner Data Register - TADR (16)H
CH0/4 : CHANNEL0/4
V1/8
V9
V10
V11
VIII.13 - HDLC Transmit Command Register - HTCR (18)H
READ : READ COMMAND MEMORY
CH0/4 : These five bits define one of 32 channels.
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bit15
bit15
CH4
V11
CH3
V10
: VALIDATION
: VALIDATION SUBCHANNEL
: DIRECT MHDLC ACCESS
: VALIDATION of CB pin
These five bits define one of 32 channels associated to TIME SLOT defined by the previous
Register (TAAR).
The logical channel CHx is constituted by each subchannel 1 to 8 and validated by V1/8 bit
V 9 = 1, each V1/8 bit is taken into account once every 250ms.
In transmit direction, data is transmitted consecutively during the time slot of the current frame
and during the same time slot of the next frame.Id est.: the same data is transmitted in two
consecutive frames.
In receive direction, HDLC controller fetches data during the time slot of the current frame and
ignores data during the same time slot of the next frame.
V 9 = 0, each V1/8 bit is taken into account once every 125ms.
If V10 = 1, the Rx HDLC Controller receives data issued from DIN8 input during the current time
slot (bits validated by V1/8) and DOUT6 output transmits data issued from the Tx HDLC
Controller.
If V10 = 0, the Rx HDLC Controller receives data issued from the matrix output 7 during the
current time slot ; DOUT6 output delivers data issued from the matrix output 6 during the same
current time slot.
N.B : If D7 = 1, (see ”General Configuration Register GCR (02)H”) the Tx HDLC controller is
connected to matrix input 7 continuously so the HDLC frames can be sent to any DOUT (i.e.
DOUT0 to DOUT7).
This bit is not taken into account if CSMA = 1 (HDLC Transmit Command Register).
if CSMA = 0 :
V11 = 1, Contention Bus pin is validated and Echo pin (which is an input) is not taken into
account.
V11 = 0, ContentionBus pin is high impedance during the current time slot (This pin is an open
drain output).
READ = 1, READ COMMAND MEMORY.
READ = 0, WRITE COMMAND MEMORY.
CH2
V9
CH1
V8
CH0
V7
READ
V6
Nu
V5
After reset (0000)
After reset (0000)
bit8
CF
bit8
V4
PEN
bit7
bit7
V3
CSMA
H
H
V2
NCRC
V1
CH4
F
CH3
P1
CH2
P0
CH1
C1
bit 0
CH0
bit 0
C0