ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 73

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

DIVN = 1 and LOCK8K = 1: (Alternate direct-lock frequency decode)
FREQ[3:0] Default Values:
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 and 5 to 0: Input Clock Valid Control (IC8 and IC[6:1]). These control bits can be used to force input
clocks to be considered invalid. If a clock is invalidated by one of these control bits it will not appear in the priority
table in the PTAB1 and PTAB2 registers, even if the clock is otherwise valid. These bits are useful when system
software needs to force clocks to be invalid in response to OAM commands. Note that setting a VALCR bit low has
no effect on the corresponding bit in the
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0: Input Clock Valid Control (IC9). This bit has the same behavior as the bits in
clock.
Rev: 012108
____________________________________________________________________________________________ DS3102
ICR1–ICR4: 0000b
ICR5–ICR9: 0011b
0 = Force invalid
1 = Do not force invalid; determine validity normally
0000 = 10MHz (internally divided down to 5MHz)
0001 = 25MHz (internally divided down to 5MHz)
0010 = 62.5MHz (internally down to 31.25MHz)
0011 = 125MHz (internally down to 31.25MHz)
0100 = 156.25MHz (differential inputs only; internally divided down to 31.25MHz)
0101–1111 = undefined
IC8
—
7
1
7
0
—
—
6
0
6
0
VALCR1
Input Clock Valid Control Register 1
30h
VALCR2
Input Clock Valid Control Register 2
31h
VALSR
IC6
—
5
1
0
5
registers. See Section 7.6.2.
IC5
—
4
1
4
0
IC4
—
3
1
3
0
IC3
—
2
1
2
0
VALCR1
IC2
—
1
1
but for the IC9 input
1
0
73 of 141
IC1
IC9
0
1
0
1