ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 35

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

____________________________________________________________________________________________ DS3102
During the recalibration process the device puts the DPLL into mini-holdover, internally ramps the phase offset to
zero, resets all clock dividers, ramps the phase offset to the value stored in the
OFFSET
registers, and switches
the DPLL out of mini-holdover. If the
OFFSET
registers are written during the recalibration process, the process
ramps the phase offset to the new offset value.
7.7.10 Frequency and Phase Measurement
When the T4 DPLL is not needed to generate an output frequency locked to an input clock, it can measure precise
frequency by locking onto any input. It can also measure phase between the T0 selected reference and any input
by setting the T0CR1.T4MT0 bit. The T4 APLL can still be used to clean up jitter on a synthesized clock from the
T0 DPLL. When the T0CR1.T4MT0 bit is set the T4 DPLL goes to the free-run state.
Standard input clock frequency monitoring is described in Section 7.5.1. The input clock monitors report measured
frequency with 3.8ppm resolution. More accurate measurement of frequency and phase can be accomplished
using the DPLLs. The T0 DPLL is always monitoring its selected reference, but if the T4 DPLL is not otherwise
used to lock to an input, it can be configured as a high-resolution phase monitor. The REFCLK signal accuracy
after being adjusted with MCLKFREQ is used for the frequency reference. Software can then connect the T4 DPLL
to various input clocks on a rotating basis to measure phase between the T0 DPLL input and another input. See
the T4FORCE field of MCR4.
DPLL frequency measurements can be read from the FREQ field spanning registers FREQ1, FREQ2, and FREQ3.
This field indicates the frequency of the selected reference for either the T0 DPLL or the T4 DPLL, depending on
the setting of the T4T0 bit in MCR11. This frequency measurement has a resolution of 0.0003068ppm over a
±80ppm range. The value read from the FREQ field is the DPLL’s integral path value, which is an averaged
measurement with an averaging time inversely proportional to DPLL bandwidth.
DPLL phase measurements can be read from the PHASE field spanning registers
PHASE1
and PHASE2. This
field indicates the phase difference seen by the phase detector for either the T0 DPLL or the T4 DPLL, depending
on the setting of the T4T0 bit in MCR11. This phase measurement has a resolution of approximately 0.703 degrees
and is internally averaged with a -3dB attenuation point of approximately 100Hz. Thus, for low DPLL bandwidths,
the PHASE field gives input phase wander in the frequency band from the DPLL corner frequency up to 100Hz.
This information could be used by software to compute a crude MTIE measurement.
For the T0 DPLL the PHASE field always indicates the phase difference between the selected reference and the
internal feedback clock. The T4 DPLL, however, can be configured to measure the phase difference between two
input clocks. When T0CR1:T4MT0 = 1, the T4 DPLL locking capability is disabled, and the T4 phase detector is
configured to compare the T0 DPLL selected reference with the T4 DPLL selected reference. Any input clock can
then be forced to be the T4 DPLL selected reference using the T4FORCE field of MCR4. This feature can be used,
for example, to measure the phase difference between the T0 DPLL’s selected reference and its next highest
priority reference. Software could compute MTIE and TDEV with respect to the T0 DPLL selected reference for any
or all the other input clocks.
When comparing the phase of the T0 and T4 selected references by setting T0CR1:T4MT0 = 1, several details
must be considered. In this mode, the T4 path receives a copy of the T0 selected reference, either directly or
through a divider to 8kHz. If the T4 selected reference is divided down to 8kHz using LOCK8K or DIVN modes (see
Section 7.4.2), the copy of the T0 selected reference is also divided down to 8kHz. If the T4 selected reference is
configured for direct-lock mode, the copy of the T0 selected reference is not divided down and must be the same
frequency as the T4 selected reference. See
Table 7-6
for more details. (While T0CR1:T4MT0 = 1, the T0 path
continues to lock to the T0 selected reference in the manner specified in the corresponding
ICR
register.)
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