ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 30

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

____________________________________________________________________________________________ DS3102
DPLL when it was in the locked state. The device can be configured for manual or automatic holdover as described
in the following subsections. When at least one input clock has been declared valid, the state machine immediately
transitions from holdover to the prelocked 2 state and tries to lock to the highest priority valid clock.
7.7.1.6.1 Automatic Holdover
For automatic holdover (FRUNHO = 0 in MCR3), the device can be further configured for instantaneous mode or
averaged mode. In instantaneous mode (AVG = 0 in HOCR3), the holdover frequency is set to the DPLL’s current
frequency 50ms to 100ms before entry into holdover (i.e., the value of the FREQ field in the FREQ1, FREQ2, and
FREQ3
registers when MCR11:T4T0 = 0). The FREQ field is the DPLL’s integral path and, therefore, is an average
frequency with a rate of change inversely proportional to the DPLL bandwidth. The DPLL’s proportional path is not
used in order to minimize the effect of recent phase disturbances on the holdover frequency.
In averaged mode (AVG = 1 in
HOCR3
and MANHO = 0 in MCR3), the holdover frequency is set to an internally
averaged value. During locked operation the frequency indicated in the FREQ field is internally averaged. The
FAST bit in HOCR3 determines the period of this averaging. When FAST = 1, the frequency is averaged for a
period of approximately 8 minutes. When FAST = 0 (slow), the frequency is averaged for a period of approximately
110 minutes. The T0 DPLL indicates that it has acquired valid holdover values by setting the FHORDY and
SHORDY status bits in
VALSR2
(real-time status) and
MSR4
(latched status). If FAST = 0 and the T0 DPLL must
enter holdover before the 110-minute average is available, the 8-minute average is used, if available. Otherwise,
the instantaneous value from the integral path is used. If FAST = 1 and the T0 DPLL must enter holdover before
the 8-minute average is available, an instantaneous value of 50ms to 100ms old from the integral path is used
instead.
7.7.1.6.2 Manual Holdover
For manual holdover (MANHO = 1 in MCR3), the holdover frequency is set by the HOFREQ field in the HOCR1,
HOCR2, and
HOCR3
registers. The HOFREQ field has the same size and format as the current frequency field
(FREQ[18:0] in the FREQ1, FREQ2, and
FREQ3
registers). If desired, software can, during locked operation, read
the current frequency from FREQ, filter or average it over time, and write the resulting holdover frequency to
HOFREQ. The FREQ field is derived from the DPLL’s integral path, and thus can be considered an average
frequency with a rate of change inversely proportional to the DPLL bandwidth.
To combine internal averaging with additional software filtering, the HOFREQ field can be configured to read out
the internally averaged frequency when RDAVG = 1 in the
HOCR3
register. This averaged value can be read from
HOFREQ regardless of the current holdover mode. The FAST bit in
HOCR3
specifies whether the value read is
from the fast averager or the slow averager.
7.7.1.7 Mini-Holdover
When the selected reference fails, the fast activity monitor (Section 7.5.3) isolates the T0 DPLL from the reference
within one or two clock cycles to avoid adverse effects on the DPLL frequency. When this fast isolation occurs, the
DPLL enters a temporary mini-holdover mode, with a frequency as specified by the MINIHO field of HOCR3. Mini-
holdover lasts until the selected reference returns or a new input clock has been chosen as the selected reference
or the state machine enters the holdover state. If the manual holdover mode is set (MANHO = 1 in MCR3), the
MINIHO field of
HOCR3
is ignored and the mini-holdover frequency is the same as the manual holdover frequency.
7.7.2 T4 DPLL State Machine
The T4 DPLL state machine is similar to the T0 DPLL, as shown in
Figure
7-3. The T4 DPLL states are similar to
the equivalent states of the T0 DPLL, but the only state indicator is the T4LOCK bit in the
OPSTATE
register. Note
that the T4 DPLL only operates in revertive switching mode. The full-holdover and mini-holdover modes are
instantaneous (see the first paragraph of Section 7.7.1.6.1).
Rev: 012108
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