ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 59

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 and 5 to 0: Input Clock Status Change (IC8 and IC[6:1]). Each of these latched status bits is set to 1
when the corresponding
enabled (MCR10:SOFTEN = 1), each of these latched status bits is also set to 1 when the corresponding SOFT bit
in the
the
on the INTREQ pin if the corresponding interrupt enable bit is set in the
clock validation/invalidation criteria.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: T0 DPLL State Change (STATE). This latched status bit is set to 1 when the operating state of the T0 DPLL
changes. STATE is cleared when written with a 1 and not set again until the operating state changes again. When
STATE is set it can cause an interrupt request on the INTREQ pin if the STATE interrupt enable bit is set in the
IER2
Section 7.7.1.
Bit 6: Selected Reference Failed (SRFAIL). This latched status bit is set to 1 when the selected reference to the
T0 DPLL fails, (i.e., no clock edges in two UI). SRFAIL is cleared when written with a 1. When SRFAIL is set it can
cause an interrupt request on the INTREQ pin if the SRFAIL interrupt enable bit is set in the
is not set in free-run mode or holdover mode. See Section 7.5.3.
Bit 0: Input Clock Status Change (IC9). This latched status bit is set to 1 when the corresponding
bit changes state (set or cleared). If soft frequency limit alarms are enabled (MCR10:SOFTEN = 1), this bit is also
set to 1 when the corresponding SOFT bit in the
when written with a 1 and not set again until either the
set it can cause an interrupt request on the INTREQ pin if the corresponding interrupt enable bit is set in the
register. See Section
Rev: 012108
____________________________________________________________________________________________ DS3102
VALSR1
register. The current operating state can be read from the T0STATE field of the
ISR
registers changes state (set or cleared). Each bit is cleared when written with a 1 and not set again until
bit changes state again. When one of these latched status bits is set it can cause an interrupt request
STATE
IC8
7
0
7
1
7.5
for input clock validation/invalidation criteria.
VALSR1
SRFAIL
6
0
—
6
0
MSR1
Master Status Register 1
05h
MSR2
Master Status Register 2
06h
status bit changes state (set or cleared). If soft frequency limit alarms are
—
IC6
5
0
5
1
ISR
—
4
0
registers changes state (set or cleared). This bit is cleared
VALSR2
IC5
4
1
bit or the SOFT bit changes state. When this bit is
—
IC4
3
0
3
1
IER1
register. See Section
IC3
2
1
—
2
0
OPSTATE
IER2
IC2
1
1
—
1
0
register. SRFAIL
VALSR
register. See
7.5
59 of 141
IC1
for input
IC9
0
1
0
1
status
IER2