ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 66

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Soft Frequency Limit Alarm for Input Clock 2 (SOFT2). This real-time status bit indicates a soft frequency
limit alarm for input clock 2. If IC2 is the selected reference, SOFT2 is set to 1 when the frequency of IC2 is greater
than or equal to the soft limit set in the
when the frequency of IC2 is greater than or equal to the soft limit set in the
disabled by default but can be enabled by setting SOFTEN = 1 in the
invalidate an input clock. See Section 7.5.1.
Bit 6: Hard Frequency Limit Alarm for Input Clock 2 (HARD2). This real-time status bit indicates a hard
frequency limit alarm for input clock 2. If IC2 is the selected reference, HARD2 is set to 1 when the frequency of
IC2 is greater than or equal to the hard limit set in the
is set to 1 when the frequency of IC2 is greater than or equal to the hard limit set in the
are enabled by default but can be disabled by setting HARDEN = 0 in the
IC2 status bit in the
Bit 5: Activity Alarm for Input Clock 2 (ACT2). This real-time status bit is set to 1 when the leaky bucket
accumulator for IC2 reaches the alarm threshold specified in the
BUCKET field of ICR1). An activity alarm clears the IC2 status bit in the
clock. See Section 7.5.2.
Bit 4: Phase-Lock Alarm for Input Clock 2 (LOCK2). This status bit is set to 1 if IC2 is the selected reference
and the T0 DPLL cannot phase lock to IC2 within the duration specified in the
seconds). A phase lock alarm clears the IC2 status bit in VALSR1, invalidating the IC2 clock. If LKATO = 1 in
MCR3
System software can clear LOCK4 by writing 0 to it, but writing 1 is ignored. See Section 7.7.1.
Bit 3: Soft Frequency Limit Alarm for Input Clock 1 (SOFT1). This bit has the same behavior as the SOFT2 bit
but for the IC1 input clock.
Bit 2: Hard Frequency Limit Alarm for Input Clock 1 (HARD1). This bit has the same behavior as the HARD2 bit
but for the IC1 input clock.
Bit 1: Activity Alarm for Input Clock 1 (ACT1). This bit has the same behavior as the ACT2 bit but for the IC1
input clock.
Bit 0: Phase-Lock Alarm for Input Clock 1 (LOCK1). This bit has the same behavior as the LOCK2 bit but for the
IC1 input clock.
Rev: 012108
____________________________________________________________________________________________ DS3102
then LOCK2 is automatically cleared after a timeout period of 128 seconds. LOCK2 is a read/write bit.
SOFT2
7
0
VALSR1
HARD2
register, invalidating the IC2 clock. See section 7.5.1.
6
1
ISR1
Input Status Register 1
10h
SRLIMIT
ACT2
5
1
register. If IC2 is not the selected reference then SOFT2 is set to 1
LOCK2
SRLIMIT
4
0
register. If IC2 is not the selected reference HARD2
LBxU
SOFT1
0
3
register (where x in LBxU is specified in the
MCR10
MCR10
VALSR1
HARD1
2
1
PHLKTO
ILIMIT
register. A hard alarm clears the
register. A soft alarm does not
register, invalidating the IC2
ILIMIT
register. Soft alarms are
register (default = 100
ACT1
register. Hard alarms
1
1
LOCK1
66 of 141
0
0