ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 47

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Table 7-17. External Frame-Sync Mode and Source
Note 1: That is, when OPSTATE:T0STATE= 100.
Note 2: X = Don’t care.
Note 3: None of the SYNCn pins is used. The internal 2kHz alignment generators free-run at their existing alignment. See Section 7.9.2.5.
Note 4: When SOURCE = 11XX, selection and enable of SYNCn pins is automatic regardless of the setting of AEFSEN. In this mode the
AEFSEN bit is retasked to specify whether or not MCR3:EFSEN is automatically cleared when the T0 DPLL’s selected reference changes.
7.9.2.2 Sampling
By default the external frame-sync signal on the enabled SYNCn pin is first sampled on the rising edge of the
selected reference. This gives the most margin, given that the SYNCn signal is falling-edge aligned with the
selected reference since both come from the master device. The expected timing of the SYNCn signal with respect
to the sampling clock can be adjusted from 0.5 cycles early to 1 cycle late using the FSCR2:PHASEn[1:0] field.
7.9.2.3 Resampling
The SYNCn signal is then resampled by an internal clock derived from the T0 DPLL. The resampling resolution is a
function of the frequency of the selected reference and FSCR2:OCN. When OCN = 0, the resampling resolution is
6.48MHz, which gives the highest sampling margin and also aligns clocks at 6.48MHz and multiples thereof. When
OCN = 1, if the selected reference is 19.44MHz the resampling resolution is 19.44MHz. If the selected reference is
38.88MHz the resampling resolution is 38.88MHz. The selected reference must be either 19.44MHz or 38.88MHz.
7.9.2.4 Qualification
The SYNCn signal is qualified when it has consistent phase and correct frequency. Specifically, it is qualified when
its significant edge has been found at exact 2kHz boundaries (when resampled as previously described) for 64
SYNCn cycles in a row. It is disqualified when one significant edge is not found at the 2kHz boundary.
7.9.2.5 Output Clock Alignment
When the T0 DPLL is locked, external frame sync is enabled and the SYNCn signal is qualified, the SYNCn signal
can be used to falling-edge align the T0 DPLL derived output clocks. Output clocks FSYNC and MFSYNC share a
2kHz alignment generator, while the rest of the T0 DPLL derived output clocks share a second 2kHz alignment
generator. When external frame sync is not enabled or the SYNCn signal is not qualified, these 2Hz alignment
generators free-run with their existing 2kHz alignments. When external frame sync is enabled and the SYNCn
signal is qualified, the FSYNC/MFSYNC 2kHz alignment generator is always synchronized by SYNCn, and,
therefore, FSYNC and MFSYNC are always falling-edge aligned with SYNCn. When FSCR2:INDEP = 0, the T0
DPLL 2kHz alignment generator is also synchronized with the FSYNC/MFSYNC 2kHz alignment generator to
falling-edge align all T0-derived output clocks with SYNCn. When INDEP = 1, the T0 DPLL 2kHz alignment
Rev: 012108
____________________________________________________________________________________________ DS3102
LOCKED
T0 DPLL
0
1
1
1
1
1
EFSEN
MCR3:
X
0
1
1
1
SOURCE
FSCR3:
<>11XX
<>11XX
XXXX
XXXX
11XX
2
AEFSEN
MCR3:
X
X
X
0
1
4
SYNCSRC
FSCR1:
XXX
XXX
XXX
XXX
0XX
1X0
1X1
10X
11X
All other cases
<>FSCR3:
IC3 or IC5
IC4 or IC6
SOURCE
SOURCE
=FSCR3:
SELREF
PTAB1:
XXXX
XXXX
XXXX
IC3
IC4
IC5
IC6
IC9
IC2
SYNC1 Manual
FRAME-SYNC
SYNC1 Auto
SYNC123
Disabled
Disabled
MODE
(Auto
4
)
FRAME-SYNC
SOURCE
Internal
Internal
SYNC1
SYNC1
Internal
SYNC1
SYNC2
SYNC1
SYNC2
SYNC1
SYNC2
SYNC3
SYNC3
Internal
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