ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 102

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 7 to 4: Output Frequency of OC6 (OFREQ6[3:0]). This field specifies the frequency of output clock output
OC6. The frequencies of the T0 APLL and T4 APLL are configured in the
Digital1 and Digital2 frequencies are configured in the
is controlled by the value of the OCR5.AOF6 bit.
AOF6 = 0: (standard decodes)
AOF6 = 1: (alternate decodes)
Bits 3 to 0: Output Frequency of OC5 (OFREQ5[3:0]). This field specifies the frequency of output clock OC5.
The frequencies of the T0 APLL and T4 APLL are configured in the
Digital2 frequencies are configured in the
by the value of the OCR5.AOF5 bit.
AOF5 = 0: (standard decodes)
Rev: 012108
____________________________________________________________________________________________ DS3102
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = T0 APLL frequency divided by 2
0100 = Digital1 (see
0101 = T0 APLL frequency
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
1010 = T0 APLL frequency divided by 4
1011 = T4 APLL frequency divided by 64
1100 = T4 APLL frequency divided by 48
1101 = T4 APLL frequency divided by 16
1110 = T4 APLL frequency divided by 8
1111 = T4 APLL frequency divided by 4
0000 = Output disabled (i.e., low)
0001 = T4 APLL frequency divided by 5
0010 = T4 APLL frequency divided by 2
0011 = T4 APLL frequency
0100 = T0 APLL2 frequency divided by 5
0101 = T0 APLL2 frequency divided by 2
0110 = T0 APLL2 frequency
0111 = T4 selected reference (after dividing)
1000 = T0 selected reference (after dividing)
1001–1111 = undefined
0000 = Output disabled (i.e., low)
0001 = 2kHz
0010 = 8kHz
0011 = Digital2 (see
0100 = Digital1 (see
0101 = T0 APLL frequency divided by 48
0110 = T0 APLL frequency divided by 16
0111 = T0 APLL frequency divided by 12
1000 = T0 APLL frequency divided by 8
1001 = T0 APLL frequency divided by 6
7
1
Table
Table
Table
OFREQ6[3:0]
6
0
OCR3
Output Configuration Register 3
62h
7-8)
7-9)
7-8)
MCR7
5
0
register. See Section 7.8.2.3. The decode of this field is controlled
MCR7
4
0
register. See Section 7.8.2.3. The decode of this field
T0CR1
3
0
and
T0CR1
T4CR1
2
1
OFREQ5[3:0]
and
registers. The Digital1 and
T4CR1
1
0
registers. The
102 of 141
0
0