ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 39

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

DIG2F[1:0] field in MCR7. DIG1 and DIG2 can be independently configured for any of the frequencies shown in
Table 7-8
The APLL DFS blocks and their associated output APLLs and output dividers can generate many different
frequencies. The T0 APLL DFS and the T0 APLL2 DFS are always connected to the T0 DPLL. The T4 APLL DFS
can be connected to either the T0 DPLL or the T4 DPLL depending on T0CR1:T4APT0 and MCR4:LKT4T0. The
T0 APLL frequencies that can be generated are listed in
312.500MHz. The T4 APLL frequencies that can be generated are listed in
can be generated from the APLL circuits are listed in
The T4 APLL is disabled and powered down when T4CR1:T4FREQ = 0000 and T0CR1:T4APT0 = 0. In this mode
all outputs connected to the T4 APLL are driven low.
Together the T0 APLL, T0 APLL2, and T4 APLL can simultaneously generate SONET/SDH clock rates, Gigabit
Ethernet clock rates (e.g., 125MHz), and 10G Ethernet clock rates (e.g., 156.25MHz), all locked to the same
selected reference. This capability supports mixed SONET/SDH and Synchronous Ethernet line cards.
7.8.2.3 OC1 to OC7 Configuration
The following is a step-by-step procedure for configuring the frequencies of output clocks OC1 to OC7:
Table 7-15
the T4 APLL to obtain each frequency.
Table 7-8. Digital1 Frequencies
Rev: 012108
____________________________________________________________________________________________ DS3102
SETTING IN
DIG1F[1:0]
MCR7
1) Determine whether the T4 APLL must be independent of the T0 DPLL. If the T4 APLL must be
2) Use
3) Determine from
4) Configure the T0FREQ field in register
5) Using
00
01
10
11
00
01
10
11
and
lists all standard frequencies for the output clocks and specifies how to configure the T0 APLL and/or
independent, set T4APT0 = 0 in register T0CR1. If the T4 APLL must be locked to the T0
DPLL, set T4APT0 = 1.
can only generate one set of output frequencies. (In SONET/SDH equipment, the T0 APLL is
typically configured for a frequency of 311.04MHz to get 19.44MHz and/or 38.88MHz output
clocks to distribute to system line cards.)
chosen in step 2.
frequency determined in step 3. Configure the T4FREQ field in register
Table 7-13
DPLL, the T4APT0 and T0FT4 fields in
7-13.
the OFREQn fields of registers
Table
Table 7-10
Table 7-10
7-9, respectively.
SETTING IN
for the T4 APLL frequency determined in step 3. If the T4 APLL is locked to the T0
DIG1SS
MCR6
0
0
0
0
1
1
1
1
Table 7-10
to select a set of output frequencies for each APLL, T0 and T4. Each APLL
and
Table
Table 7-15
FREQUENCY
the T0 and T4 APLL frequencies required for the frequency sets
7-14, configure the frequencies of output clocks OC1 to OC7 in
OCR1
16.384
12.352
(MHz)
2.048
4.096
8.192
1.544
3.088
6.176
to
also indicates the expected jitter amplitude for each frequency.
OCR4
Table
T0CR1
T0CR1
(pk-pk ns,
7-10.
and the AOFn bit in the
JITTER
must also be configured as shown in
typ)
as shown in
< 1
< 1
< 1
< 1
< 1
< 1
< 1
< 1
Table
7-11. The T0 APLL2 frequency is always
Table
Table 7-11
7-13. The output frequencies that
OCR5
T4CR1
for the T0 APLL
register.
as shown in
Table
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