ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 67

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Soft Frequency Limit Alarm for Input Clock 4 (SOFT4). This real-time status bit indicates a soft frequency
limit alarm for input clock 4. If IC4 is the selected reference then SOFT4 is set to 1 when the frequency of IC4 is
greater than or equal to the soft limit set in the
set to 1 when the frequency of IC4 is greater than or equal to the soft limit set in the
disabled by default but can be enabled by setting SOFTEN = 1 in the
invalidate an input clock. See Section 7.5.1.
Bit 6: Hard Frequency Limit Alarm for Input Clock 4 (HARD4). This real-time status bit indicates a hard
frequency limit alarm for input clock 4. If IC4 is the selected reference then HARD4 is set to 1 when the frequency
of IC4 is greater than or equal to the hard limit set in the
HARD4 is set to 1 when the frequency of IC4 is greater than or equal to the hard limit set in the
Hard alarms are enabled by default but can be disabled by setting HARDEN = 0 in the
alarm clears the IC4 status bit in the
Bit 5: Activity Alarm for Input Clock 4 (ACT4). This real-time status bit is set to 1 when the leaky bucket
accumulator for IC4 reaches the alarm threshold specified in the
BUCKET field of ICR4). An activity alarm clears the IC4 status bit in the
clock. See Section 7.5.2.
Bit 4: Phase-Lock Alarm for Input Clock 4 (LOCK4). This status bit is set to 1 if IC4 is the selected reference
and the T0 DPLL cannot phase lock to IC4 within the duration specified in the
seconds). A phase-lock alarm clears the IC4 status bit in VALSR1, invalidating the IC4 clock. If LKATO = 1 in
MCR3
System software can clear LOCK4 by writing 0 to it, but writing 1 is ignored. See Section 7.7.1.
Bit 3: Soft Frequency Limit Alarm for Input Clock 3 (SOFT3). This bit has the same behavior as the SOFT4 bit
but for the IC3 input clock.
Bit 2: Hard Frequency Limit Alarm for Input Clock 3 (HARD3). This bit has the same behavior as the HARD4 bit
but for the IC3 input clock.
Bit 1: Activity Alarm for Input Clock 3 (ACT3). This bit has the same behavior as the ACT4 bit but for the IC3
input clock.
Bit 0: Phase-Lock Alarm for Input Clock 3 (LOCK3). This bit has the same behavior as the LOCK4 bit but for the
IC3 input clock.
Rev: 012108
____________________________________________________________________________________________ DS3102
then LOCK4 is automatically cleared after a timeout period of 128 seconds. LOCK4 is a read/write bit.
SOFT4
7
0
HARD4
6
1
ISR2
Input Status Register 2
11h
VALSR1
ACT4
5
1
register, invalidating the IC4 clock. See section 7.5.1.
SRLIMIT
LOCK4
register. If IC4 is not the selected reference then SOFT4 is
4
0
SRLIMIT
LBxU
SOFT3
register. If IC4 is not the selected reference then
0
3
register (where x in LBxU is specified in the
MCR10
VALSR1
HARD3
2
1
PHLKTO
register. A soft alarm does not
ILIMIT
register, invalidating the IC4
MCR10
register. Soft alarms are
register (default = 100
ACT3
1
1
register. A hard
ILIMIT
LOCK3
67 of 141
register.
0
0