ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 45

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

7.8.2.5 Custom Output Frequencies
In addition to the many standard frequencies available in the device, any of the seven output DFS blocks can be
configured to generate a custom frequency. Possible custom frequencies include any multiple of 2kHz up to
77.76MHz and any multiple of 8kHz up to 311.04MHz. (An APLL must be used to achieve frequencies above
77.76MHz.) Any of the programmable output clocks can be configured to output the custom frequency or
submultiples thereof. Contact the factory at
7.9
Most high-reliability SONET/SDH systems require two identical timing cards for equipment redundancy. The
DS3102 directly supports this requirement. In such a system, one timing card is designated the master while the
other is designated the slave. The rest of the system, outside the timing cards, is set up to take timing from the
master normally, but to automatically switch to taking timing from the slave if the master fails. To avoid excessive
phase transients when switching between master timing and slave timing, the clocks from the master and the slave
must be frequency-locked and usually phase-locked as well. To accomplish this requires a method involving both
static configuration and ongoing oversight by system software.
Table 7-16. Equipment Redundancy Methodology
7.9.1 Master-Slave Output Clock-Phase Alignment
When the T0 DPLL is direct-locked to a selected reference with frequency Fref, any output clocks derived from T0
with frequency Fref are phase-aligned with the selected reference (if phase build-out is disabled). Any output clocks
derived from T0 with frequency greater than Fref are “falling edge aligned” with the frequency Fref output clock.
Any output clocks derived from T0 with frequency less than Fref may or may not be aligned, depending on whether
their frequencies are integer submultiples of f. These statements also apply to output clocks derived from the T4
DPLL.
Rev: 012108
____________________________________________________________________________________________ DS3102
1.
2.
3.
4.
5.
6.
Note 1:
Equipment Redundancy Configuration
The various clock sources available in the system should be wired to the same pins on the slave as on
the master, except:
A. One output clock from the master device should be wired to an input clock on the slave.
B. One output clock from the slave device should be wired to an input clock on the master.
The input clock priorities
paths, except:
A. The master output clock is the highest priority input on the slave.
B. The slave output clock is disabled (priority 0) on the master.
This ensures that the frequency of the slave matches the frequency of the master.
Any input declared invalid in one device
other device
properly, the slave locks to the master, and when the master fails, the slave locks to the input clock the
master was previously locked to.
The slave’s T0 DPLL bandwidth should be set higher than the master’s bandwidth (T0LBW,
registers) to ensure that the slave follows any transients coming from the master. (70 Hz is
recommended.)
Phase build-out should be disabled (MCR10:PBOEN = 0) on the slave when it is locked to the master
to ensure that the slave maintains phase lock with the master. This also allows the use of phase offset
(OFFSET
Revertive mode should be enabled on the slave (REVERT = 1 in MCR3) to ensure the slave switches
from any other reference to the master as soon as the master’s clock is valid.
This must be done for the slave’s T0 path, but is not necessary for the slave’s T4 path. In the slave’s T4 path the input clock
priorities should match those of the master except the input connected to the master’s output clock should be disabled. This
causes the slave’s T4 path to only lock to external references.
registers) to compensate for delays between master and slave.
(VALCR
registers). This and item 2 together ensure that when the master is performing
(IPR
registers) on master and slave should be identical, for both T0 and T4
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(VALSR
registers) must be marked invalid by software in the
Table 7-16
lists the elements of this methodology.
for help with custom frequencies.
(1)
T0ABW
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