ds3102 Maxim Integrated Products, Inc., ds3102 Datasheet - Page 18

• Manufacturer Part Number: ds3102
• Description: Stratum 3 Timing Card Ic With Synchronous Ethernet Support
• Manufacturer: Maxim Integrated Products, Inc.

Typically, the internal state machine controls the T0 DPLL, but manual control by system software is also available.
The T4 DPLL has a simpler state machine that software cannot directly control. In either DPLL, however, software
can override the DPLL logic using manual reference selection.
The output and feedback synthesizers are locked to either the T0 DPLL or the T4 DPLL. Most of the output signals
that are locked to the same DPLL are always aligned to the falling edge at 2kHz.
The outputs of the T0 DPLL and the T4 DPLL can be connected to seven output DFS engines. See
Three of these output DFS engines are associated with high-speed APLLs that multiply the DPLL clock rate and
filter DPLL output jitter. The outputs of the APLLs are divided down to make a wide variety of possible frequencies
available at the output clock pins. T0 APLL and T0 APLL2 are always locked to the T0 DPLL, while the T4 APLL
can lock to either the T4 DPLL or the T0 DPLL. The output frequencies from the T0 DPLL can be synchronized to
an input 2, 4, or 8kHz sync signal (SYNC1, SYNC2, or SYNC3 input pins). This synchronization to a low-frequency
input enables, among other things, two redundant timing cards to maintain output frame-sync alignment with one
another.
The OC1 to OC7 output clocks can be configured for a variety of different frequencies that are frequency and
phase-locked to either the T0 DPLL or the T4 DPLL. The OC6 and OC7 outputs are LVDS/LVPECL; OC4 and OC5
are available in both LVDS/LVPECL and 3.3V CMOS; and OC1 to OC3 are 3.3V CMOS. There are five outputs
OC1B to OC5B that can be 3.3V or 2.5V CMOS outputs. Altogether more than 60 output frequencies are possible,
ranging from 2kHz to 312.5MHz. The FSYNC output clock is always 8kHz, and the MFSYNC output clock is always
2kHz.
7.2
The 16-bit read-only ID field in the
be read from the
register set can be protected from inadvertent writes using the
7.3
The T0 DPLL, the T4 DPLL, and the output DFS engines operate from a 204.8MHz master clock. The master clock
is synthesized from a 12.800MHz clock originating from a local oscillator attached to the REFCLK pin. The stability
of the T0 DPLL in free-run or holdover is equivalent to the stability of the local oscillator. Selection of an appropriate
local oscillator is therefore of crucial importance if the telecom standards listed in
XOs or TCXOs can be used in less stringent cases, but OCXOs may be required in the most demanding
applications. Even OCXOs may need to be shielded to avoid slow frequency changes due to ambient temperature
fluctuations and drift. Careful evaluation of the local oscillator component is necessary to ensure proper
performance. Contact Maxim at
Telcordia GR-1244-CORE stability requirements for Stratum 3 are listed in
Table 7-1. GR-1244 Stratum 3 Stability Requirements Example
Note: Refer to GR-1244-CORE for additional details.
The stability of the local oscillator is very important, but its absolute frequency accuracy is less important because
the DPLLs can compensate for frequency inaccuracies when synthesizing the 204.8MHz master clock from the
local oscillator clock. The MCLKFREQ field in registers
be applied. The adjust can be from -771ppm to +514ppm in 0.0196229ppm (i.e., ~0.02ppm) steps.
The DS3102 has a watchdog circuit that causes an interrupt on the INTREQ pin when the local oscillator attached
to the REFCLK pin is significantly off frequency. The watchdog interrupt is not maskable, but is subject to the
INTCR
Rev: 012108
____________________________________________________________________________________________ DS3102
register settings. When the watchdog circuit activates, reads of any and all registers in the device will return
Device Identification and Protection
Local Oscillator and Master Clock Configuration
Drift (nontemp)
PARAMETER
Temperature
REV
register. Contact the factory to interpret this value and determine the latest revision. The
[e-mail]
ID1
and
ID2
registers is set to 0C1Eh = 3102 decimal. The device revision can
± 4.63 x 10
(± 40 x 10
STRATUM 3
± 280 x 10
MCLK1
-9
-13
PROT
/day)
/sec
-9
and
for recommended oscillators. For reference, the
MCLK2
register.
Table
specifies the frequency adjustment to
7-1.
Table 1-1
are to be met. Simple
Figure
18 of 141
7-1.