ADV7343BSTZ Analog Devices Inc, ADV7343BSTZ Datasheet - Page 74

• Manufacturer Part Number: ADV7343BSTZ
• Description: IC ENCODER VIDEO W/DAC 64-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7343BSTZ

• Applications: DVD, Blu-Ray
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: -40°C To +85°C
• Tv / Video Case Style: LQFP
• No. Of Pins: 64
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 85°C
• Operating: RoHS Compliant
• Input Format: Digital
• Output Format: Analogue
• Dac Resolution: 11bit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7342/ADV7343
COPY GENERATION MANAGEMENT SYSTEM
SD CGMS
Subaddress 0x99 to Subaddress 0x9B
The ADV7342/ADV7343 support a copy generation
management system (CGMS) conforming to the EIAJ CPR-
1204 and ARIB TR-B15 standards. CGMS data is transmitted
on Line 20 of odd fields and Line 283 of even fields. Subaddress
0x99, Bits[6:5] control whether CGMS data is output on odd or
even fields or both.
SD CGMS data can be transmitted only when the ADV7342/
ADV7343 are configured in NTSC mode. The CGMS data is 20
bits long. The CGMS data is preceded by a reference pulse of
the same amplitude and duration as a CGMS bit (see Figure 93).
ED CGMS
Subaddress 0x41 to Subaddress 0x43;
Subaddress 0x5E to Subaddress 0x6E
525p Mode
The ADV7342/ADV7343 support a copy generation manage-
ment system (CGMS) in 525p mode in accordance with EIAJ
CPR-1204-1.
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 525p
CGMS data is inserted on Line 41 and the 525p CGMS data
registers are at Subaddress 0x41, Subaddress 0x42, and Sub-
address 0x43. The ADV7342/ADV7343 also support CGMS
Type B packets in 525p mode in accordance with CEA-805-A.
When ED CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
525p CGMS Type B data is inserted on Line 40. The 525p CGMS
Type B data registers are at Subaddress 0x5E to Subaddress 0x6E.
625p Mode
The ADV7342/ADV7343 support a copy generation manage-
ment system (CGMS) in 625p mode in accordance with
IEC62375 (2004).
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p
CGMS data is inserted on Line 43. The 625p CGMS data
registers are at Subaddress 0x42 and Subaddress 0x43.
HD CGMS
Subaddress 0x41 to Subaddress 0x43;
Subaddress 0x5E to Subaddress 0x6E
The ADV7342/ADV7343 support a copy generation manage-
ment system (CGMS) in HD mode (720p and 1080i) in
accordance with EIAJ CPR-1204-2.
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 720p
CGMS data is applied to Line 24 of the luminance vertical
blanking interval.
Rev. A | Page 74 of 104
When HD CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 1080i
CGMS data is applied to Line 19 and Line 582 of the luminance
vertical blanking interval.
The HD CGMS data registers are at Subaddress 0x41, Subad-
dress 0x42, and Subaddress 0x43.
The ADV7342/ADV7343 also support CGMS Type B packets in
HD mode (720p and 1080i) in accordance with CEA-805-A.
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
720p CGMS data is applied to Line 23 of the luminance vertical
blanking interval.
When HD CGMS Type B is enabled (Subaddress 0x5E, Bit 0 = 1),
1080i CGMS data is applied to Line 18 and Line 581 of the
luminance vertical blanking interval.
The HD CGMS Type B data registers are at Subaddress 0x5E to
Subaddress 0x6E.
CGMS CRC FUNCTIONALITY
If SD CGMS CRC (Subaddress 0x99, Bit 4) or ED/HD CGMS
CRC (Subaddress 0x32, Bit 7) is enabled, the upper six CGMS
data bits, C19 to C14, which comprise the 6-bit CRC check
sequence, are automatically calculated on the ADV7342/ADV7343.
This calculation is based on the lower 14 bits (C13 to C0) of the
data in the CGMS data registers, and the result is output with
the remaining 14 bits to form the complete 20 bits of the CGMS
data. The calculation of the CRC sequence is based on the
polynomial x
If SD CGMS CRC or ED/HD CGMS CRC are disabled, all
20 bits (C19 to C0) are output directly from the CGMS registers
(CRC must be calculated by the user manually).
If ED/HD CGMS Type B CRC (Subaddress 0x5E, Bit 1) is
enabled, the upper six CGMS Type B data bits (P122 to P127)
that comprise the 6-bit CRC check sequence are automatically
calculated on the ADV7342/ADV7343. This calculation is
based on the lower 128 bits (H0 to H5 and P0 to P121) of the
data in the CGMS Type B data registers. The result is output
with the remaining 128 bits to form the complete 134 bits of the
CGMS Type B data. The calculation of the CRC sequence is
based on the polynomial x
111111.
If ED/HD CGMS Type B CRC is disabled, all 134 bits (H0 to H5
and P0 to P127) are output directly from the CGMS Type B
registers (CRC must be calculated by the user manually).
6
+ x + 1 with a preset value of 111111.
6
+ x + 1 with a preset value of