ADV7343BSTZ Analog Devices Inc, ADV7343BSTZ Datasheet - Page 33

• Manufacturer Part Number: ADV7343BSTZ
• Description: IC ENCODER VIDEO W/DAC 64-LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7343BSTZ

• Applications: DVD, Blu-Ray
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Supply Voltage Range: 1.71V To 1.89V
• Operating Temperature Range: -40°C To +85°C
• Tv / Video Case Style: LQFP
• No. Of Pins: 64
• Svhc: No SVHC (18-Jun-2010)
• Operating Temperature Max: 85°C
• Operating: RoHS Compliant
• Input Format: Digital
• Output Format: Analogue
• Dac Resolution: 11bit
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 22. Register 0x31 to Register 0x33
SR7 to
SR0
0x31
0x32
0x33
Register
ED/HD Mode
Register 2
ED/HD Mode
Register 3
ED/HD Mode
Register 4
Bit Description
ED/HD pixel data valid
Reserved
ED/HD test pattern enable
ED/HD test pattern hatch/field
ED/HD VBI open
ED/HD undershoot limiter
ED/HD sharpness filter
ED/HD Y delay with respect to the
falling edge of HSYNC
ED/HD color delay with respect to the
falling edge of HSYNC
ED/HD CGMS
ED/HD CGMS CRC
ED/HD Cr/Cb sequence
Reserved
Sinc compensation filter on DAC 1,
DAC 2, DAC 3
Reserved
ED/HD chroma SSAF
ED/HD chroma input
ED/HD double buffering
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7
0
1
0
1
0
1
6
0
0
1
1
0
1
0
1
5
0
1
0
1
0
0
0
0
1
0
1
Bit Number
4
0
1
0
0
1
1
0
0
3
0
1
0
1
0
1
0
0
1
2
0
1
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
Register Setting
Pixel data valid off.
Pixel data valid on.
ED/HD test pattern off.
ED/HD test pattern on.
Hatch.
Field/frame.
Disabled.
Enabled.
Disabled.
−11 IRE.
−6 IRE.
−1.5 IRE.
Disabled.
Enabled.
0 clock cycles.
One clock cycle.
Two clock cycles.
Three clock cycles.
Four clock cycles.
0 clock cycles.
One clock cycle.
Two clock cycles.
Three clock cycles.
Four clock cycles.
Disabled.
Enabled.
Disabled.
Enabled.
Cb after falling edge of HSYNC.
Cr after falling edge of HSYNC
0 must be written to these bits.
Disabled.
Enabled
0 must be written to this bit.
Disabled.
Enabled.
4:4:4.
4:2:2
Disabled.
Enabled.
ADV7342/ADV7343
Reset
Value
0x00
0x00
0x68