ADV7343BSTZ Analog Devices Inc, ADV7343BSTZ Datasheet
ADV7343BSTZ
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ADV7343BSTZ Summary of contents
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FEATURES 74.25 MHz 16-/24-bit high definition input support Compliant with SMPTE 274M (1080i), 296M (720p), and 240M (1035i) Six 11-bit, 297 MHz video DACs 16× (216 MHz) DAC oversampling for SD 8× (216 MHz) DAC oversampling for ED 4× (297 ...
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ADV7342/ADV7343 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Functional Block Diagram .............................................................. 5 Specifications ..................................................................................... 6 Power Supply and Voltage Specifications .................................. 6 Voltage Reference Specifications ................................................ 6 Input Clock ...
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Copy Generation Management System ........................................ 74 SD CGMS ..................................................................................... 74 ED CGMS..................................................................................... 74 HD CGMS .................................................................................... 74 CGMS CRC Functionality ......................................................... 74 SD Wide Screen Signaling .............................................................. 77 SD Closed Captioning .................................................................... 78 Internal Test Pattern Generation ................................................... 79 SD ...
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ADV7342/ADV7343 GENERAL DESCRIPTION The ADV7342/ADV7343 are high speed, digital-to-analog video encoders in a 64-lead LQFP package. Six high speed, 3.3 V, 11-bit video DACs provide support for composite (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard definition (SD), ...
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DGND (2) V (2) DD GND_IO VBI DATA SERVICE INSERTION V DD_IO 8-/16-/24-BIT RGB SD 4:2:2 TO 4:4:4 TO YCrCb SD MATRIX DEINTERLEAVE VIDEO DATA R RGB ASYNC BYPASS G/B YCbCr 8-/16-/24-BIT SDR/DDR ED/HD ED/HD INPUT HDTV 4:2:2 TO 4:4:4 ...
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ADV7342/ADV7343 SPECIFICATIONS POWER SUPPLY AND VOLTAGE SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 2. Parameter SUPPLY VOLTAGES DD_IO POWER SUPPLY REJECTION RATIO VOLTAGE REFERENCE SPECIFICATIONS ...
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ANALOG OUTPUT SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 5. Parameter Full-Drive Output Current (Full-Scale) ...
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ADV7342/ADV7343 DIGITAL TIMING SPECIFICATIONS— All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 8. Parameter VIDEO DATA ...
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DIGITAL TIMING SPECIFICATIONS— All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 9. Parameter VIDEO DATA AND ...
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ADV7342/ADV7343 MPU PORT TIMING SPECIFICATIONS All specifications (−40°C to +85°C), unless otherwise noted. MIN MAX Table 10. Parameter 2 1 ...
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VIDEO PERFORMANCE SPECIFICATIONS Table 12. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity 1 Differential Nonlinearity +ve 1 Differential Nonlinearity −ve STANDARD DEFINTION (SD) MODE Luminance ...
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ADV7342/ADV7343 TIMING DIAGRAMS The following abbreviations are used in Figure 2 to Figure 13: • clock high time 9 • clock low time 10 • data setup time 11 • data hold ...
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CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Cb0 Cr0 t 11 CONTROL OUTPUTS Figure 5. ED/HD-SDR Only, 16-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 001) CLKIN_A t t ...
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ADV7342/ADV7343 CONTROL INPUTS *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USIN G SUBADDRESS 0x01, BITS 1 AND 2. Figure 8. ED/HD-DDR Only, 8-Bit, 4:2:2 YCrCb ( HSYNC / VSYNC ) Pixel Input Mode (Input Mode 010) CLKIN_A CONTROL ...
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CLKIN_B P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y0 Cr0 Cb0 CLKIN_A S_HSYNC, CONTROL INPUTS S_VSYNC Cb0 Y0 Figure 11. SD and ED/HD-DDR, 8-Bit, ...
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ADV7342/ADV7343 Y OUTPUT P_HSYNC P_VSYNC P_BLANK AND b AS PER RELEVANT STANDARD PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMIN SPECIFICATION SECTION OF ...
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Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK AND b AS PER RELEVANT STANDARD PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION ...
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ADV7342/ADV7343 S_HSYNC S_VSYNC Y7 TO Y0* *SELECTED BY SUBADDRESS 0x01, BIT 7. SDA SCL Figure 18. SD Input Timing Diagram (Timing Mode ...
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ABSOLUTE MAXIMUM RATINGS Table 13. 1 Parameter V to AGND DGND PGND GND_IO DD_IO AGND to DGND AGND to PGND AGND to GND_IO DGND to PGND DGND to GND_IO PGND to ...
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ADV7342/ADV7343 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V DD_IO TEST0 TEST1 DGND Y6 Y7 TEST2 TEST3 C0 Table 15. Pin Function Descriptions Input/ Pin No. Mnemonic Output 13, 12 ...
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R I SET2 45, 35 COMP1, O COMP2 44, 43, 42 DAC 1, DAC 2, O DAC 3 39, 38, 37 DAC 4, DAC 5, O DAC 6 21 SCL I 20 SDA I/O 19 ALSB ...
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ADV7342/ADV7343 TYPICAL PERFORMANCE CHARACTERISTICS ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 21. ED 8× Oversampling, PrPb Filter (Linear) Response ...
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Y RESPONSE IN HD 4× OVERSAMPLING MODE 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 18.5 37.0 55.5 74.0 92.5 FREQUENCY (MHz) Figure 27. HD 4× Oversampling, Y Filter Response Y PASS BAND IN HD ...
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ADV7342/ADV7343 Y RESPONSE IN SD OVERSAMPLING MODE 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 33. SD, 16× Oversampling, Y Filter Response 0 –10 –20 –30 –40 –50 –60 ...
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FREQUENCY (MHz) Figure 39. SD Luma QCIF Low-Pass Filter Response 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 40. ...
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ADV7342/ADV7343 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 45. SD Chroma CIF Low-Pass Filter Response Rev Page 26 of 104 0 –10 –20 –30 –40 –50 –60 ...
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MPU PORT DESCRIPTION Devices such as a microprocessor can communicate with the ADV7342/ADV7343 through a 2-wire serial (I bus. After power-up or reset, the MPU port is configured for operation. To obtain information about communicating with the ...
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ADV7342/ADV7343 SDA SCL START ADDR R/W ACK SUBADDRESS ACK WRITE S SLAVE ADDR A(S) SEQUENCE LSB = 0 READ S SLAVE ADDR A(S) SEQUENCE S = START BIT P = STOP BIT S 9 1–7 9 1– ...
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REGISTER MAP ACCESS A microprocessor can read from or write to all registers of the ADV7342/ADV7343 via the MPU port, except for registers that are specified as read-only or write-only registers. The subaddress register determines which register the next read ...
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ADV7342/ADV7343 SR7 to SR0 Register Bit Description 0x02 Mode Register 0 Reserved HD interlace external VSYNC and Test pattern black bar. Manual CSC matrix adjust Sync on RGB RGB/YPrPb output select SD sync output enable ED/HD sync output enable 0x03 ...
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SR7 to SR0 Register Bit Description 0x0B DAC 1, DAC 2, DAC 3 Positive gain to DAC output voltage output levels Negative gain to DAC output voltage 0x0D DAC power mode DAC 1 low power enable DAC 2 low power ...
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ADV7342/ADV7343 SR7 to SR0 Register 0x17 Software reset Logic 0 or Logic 1. Table 21. Register 0x30 SR7 to SR0 Register Bit Description 0x30 ED/HD Mode ED/HD output standard Register 1 ED/HD input synchronization format ED/HD standard ...
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Table 22. Register 0x31 to Register 0x33 SR7 to SR0 Register Bit Description 0x31 ED/HD Mode ED/HD pixel data valid Register 2 Reserved ED/HD test pattern enable ED/HD test pattern hatch/field ED/HD VBI open ED/HD undershoot limiter ED/HD sharpness filter ...
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ADV7342/ADV7343 Table 23. Register 0x34 to Register 0x35 SR7 to SR0 Register Bit Description 0x34 ED/HD Mode ED/HD timing reset Register 5 ED/HD HSYNC control ED/HD VSYNC control ED/HD blank polarity ED Macrovision® enable Reserved ED/HD VSYNC/field input Horizontal/vertical 2 ...
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Table 24. Register 0x36 to Register 0x43 SR7 to SR0 Register Bit Description 2 0x36 ED/HD Y level ED/HD Test Pattern Y level 2 0x37 ED/HD Cr level ED/HD Test Pattern Cr level 2 0x38 ED/HD Test Pattern Cb level ...
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ADV7342/ADV7343 SR7 to SR0 Register Bit Description 0x54 ED/HD Gamma B6 ED/HD Gamma Curve B (Point 128) 0x55 ED/HD Gamma B7 ED/HD Gamma Curve B (Point 160) 0x56 ED/HD Gamma B8 ED/HD Gamma Curve B (Point 192) 0x57 ED/HD Gamma ...
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SR7 to SR0 Register 0x5B ED/HD Adaptive Filter Threshold A 0x5C ED/HD Adaptive Filter Threshold B 0x5D ED/HD Adaptive Filter Threshold Logic 0 or Logic 1. Table 27. Register 0x5E to Register 0x6E SR7 to SR0 ...
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ADV7342/ADV7343 Table 28. Register 0x80 to Register 0x83 SR7 to SR0 Register Bit Description 0x80 SD Mode SD standard Register 1 SD luma filter SD chroma filter 0x82 SD Mode SD PrPb SSAF Register 2 SD DAC Output 1 SD ...
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Table 29. Register 0x84 to Register 0x89 SR7 to SR0 Register Bit Description 0x84 SD Mode Reserved Register 4 SD SFL/SCR/TR mode select SD active video vength SD chroma SD burs SD color bars. SD luma/chroma swap 0x86 SD Mode ...
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ADV7342/ADV7343 SR7 to SR0 Register Bit Description 0x88 SD Mode Reserved Register 7 SD noninterlaced mode SD double buffering SD input format SD digital noise reduction SD gamma correction enable SD gamma correction curve select 0x89 SD Mode SD undershoot ...
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SR7 to SR0 Register Bit Description 0x8B SD Timing Register 1 SD HSYNC width (applicable in master modes only, that is, Subaddress 0x8A, Bit HSYNC to VSYNC delay SD HSYNC to VSYNC rising edge delay (Mode ...
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ADV7342/ADV7343 Table 31. Register 0x99 to Register 0xA5 SR7 to SR0 Register Bit Description 0x99 SD CGMS/WSS 0 SD CGMS data SD CGMS CRC SD CGMS on odd fields SD CGMS on even fields SD WSS 0x9A SD CGMS/WSS 1 ...
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SR7 to SR0 Register Bit Description 0xA4 SD DNR 1 DNR threshold Border area Block size control 0xA5 SD DNR 2 DNR input select DNR mode DNR block offset Logic 0 or Logic 1. Table 32. Register ...
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ADV7342/ADV7343 SR7 to SR0 Register Bit Description 0xBB Field count Field count Reserved Encoder version code Logic 0 or Logic 1. See the HD Interlace External P_HSYNC and P_VSYNC Considerations section for information about the first encoder ...
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Table 35. Register 0xE0 to Register 0xF1 SR7 to SR0 Register 2 Bit Description 0xE0 Macrovision MV control bits 0xE1 Macrovision MV control bits 0xE2 Macrovision MV control bits 0xE3 Macrovision MV control bits 0xE4 Macrovision MV control bits 0xE5 ...
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ADV7342/ADV7343 INPUT CONFIGURATION The ADV7342/ADV7343 support a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7342/ADV7343 default to standard definition only (SD only) on power-up. Table 36 provides an overview of all ...
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ADV7342/ADV7343 ADV7342/ ADV7343 2 S_VSYNC, MPEG2 S_HSYNC DECODER 27MHz CLKIN_A 8 YCrCb S[7:0] OR Y[7:0]* *SELECTED BY SUBADDRESS 0x01, BIT 7. Figure 51. SD Only Example Application ENHANCED DEFINITION/HIGH DEFINITION ONLY Subaddress 0x01, Bits[6:4] = 001 or 010 Enhanced definition ...
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ADV7342/ADV7343 Whether the ED/HD Y data is clocked in on the rising or falling edge of CLKIN_B is determined by Subaddress 0x01, Bits[2:1] (see the input sequence shown in Figure 52 and Figure 53). S_VSYNC, 2 S_HSYNC SD 27MHz DECODER ...
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OUTPUT CONFIGURATION The ADV7342/ADV7343 support a number of different output configurations. Table 37 to Table 40 list all possible output configurations. Table 37. SD Only Output Configurations RGB/YPrPb SD DAC SD DAC Output Select 1 Output 2 Output 1 (Subaddress ...
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ADV7342/ADV7343 DESIGN FEATURES OUTPUT OVERSAMPLING The ADV7342/ADV7343 include two on-chip phase-locked loops (PLLs) that allow for oversampling of SD, ED, and HD video data. Table 41 shows the various oversampling rates supported in the ADV7342/ADV7343. SD Only, ED Only, and ...
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HD INTERLACE EXTERNAL P_HSYNC AND P_VSYNC CONSIDERATIONS If the encoder revision code (Subaddress 0xBB, Bits[7:6 higher, the user should set Subaddress 0x02, Bit 1 to high to ensure exactly correct timing in HD interlace modes when using ...
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ADV7342/ADV7343 DISPLAY 307 NO F RESET APPLIED SC DISPLAY 307 F RESET APPLIED SC Figure 61. SD Subcarrier Phase Reset Timing Diagram (Subaddress 0x84, Bits [2:1] = 01) COMPOSITE 1 VIDEO H/L TRANSITION COUNT START 128 RTC TIME SLOT 01 ...
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In SD Timing Mode 0 (slave option), if VBI is enabled, the blanking bit in the EAV/SAV code is overwritten possible to use VBI in this timing mode as well. If CGMS is enabled and VBI is disabled, ...
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ADV7342/ADV7343 ANALOG VIDEO EAV CODE INPUT PIXELS CLOCK NTSC/PAL M SYSTEM (525 LINES/60Hz) 4 CLOCK PAL SYSTEM (625 LINES/50Hz) END OF ACTIVE VIDEO ...
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EXTENDED (SSAF) PrPb FILTER MODE 0 –10 –20 –30 –40 –50 – FREQUENCY (MHz) Figure 65. PrPb SSAF Filter If this filter is disabled, one of the chroma filters shown in Table 45 can be ...
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ADV7342/ADV7343 Table 46. Sample Color Values for EIA 770.2/EIA 770.3 ED/HD Output Standard Selection Sample Color Y Value Cr Value White 235 (0xEB) 128 Black 16 (0x10) 128 Red 81 (0x51) 240 Green 145 (0x91) 34 Blue 41 (0x29) 110 ...
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On power-up, the CSC matrix is programmed with the default values shown in Table 50. Table 50. ED/HD Manual CSC Matrix Default Values Subaddress 0x03 0x04 0x05 0x06 0x07 0x08 0x09 When the ED/HD manual CSC matrix adjust feature is ...
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ADV7342/ADV7343 The hue adjust value is calculated using the following equation: Hue Adjust (°) = 0.17578125° ( HCR where HCR is the hue adjust control register (decimal). d For example, to adjust the hue by +4°, write 0x97 to the ...
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DOUBLE BUFFERING Subaddress 0x33, Bit 7 for ED/HD; Subaddress 0x88, Bit 2 for SD Double-buffered registers are updated once per field. Double buffering improves overall performance because modifications to register settings are not made during active video but take effect ...
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ADV7342/ADV7343 SD gamma correction is enabled using Subaddress 0x88, Bit 6. SD Gamma Correction Curve A is programmed at Subaddress 0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B is programmed at Subaddress 0xB0 to Subaddress 0xB9. Gamma correction ...
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ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS Subaddress 0x40; Subaddress 0x58 to Subaddress 0x5D There are three filter modes available on the ADV7342/ADV7343: a sharpness filter mode and two adaptive filter modes. ED/HD Sharpness Filter Mode To enhance or attenuate ...
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ADV7342/ADV7343 CH1 500mV REF A 500mV 4.00µs Figure 73. ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES Sharpness Filter Application The ED/HD ...
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When the adaptive filter mode is changed to Mode B (Subaddress 0x35, Bit 6), the output shown in Figure 76 can be obtained. Figure 76. Output Signal from ED/HD Adaptive Filter (Mode B) SD DIGITAL NOISE REDUCTION Subaddress 0xA3 to ...
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ADV7342/ADV7343 APPLY DATA APPLY BORDER CORING GAIN CORING GAIN ...
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LUM A CHANNEL WITH ACTIVE VIDEO EDGE DISABLED 100 IRE 0 IRE Figure 81. Example of Active Video Edge Functionality VOLTS IRE:FLT 100 0 – Figure 82. Example of Video Output with Subaddress ...
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ADV7342/ADV7343 EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL For timing synchronization purposes, the ADV7342/ADV7343 are able to accept either EAV/SAV time codes embedded in the input pixel data or external synchronization signals provided on the S_HSYNC , S_VSYNC , P_HSYNC , ...
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Table 58. S_VSYNC Output Control , 1 2 ED/HD VSYNC ED/HD Input ED/HD Sync Sync Format Control Output Enable (Subaddress (Subaddress (Subaddress 0x30, Bit 2) 0x34, Bit 2) 0x02, Bit ...
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ADV7342/ADV7343 SLEEP MODE Subaddress 0x00, Bit 0 In sleep mode, most of the digital I/O pins of the ADV7340/ ADV7341 are disabled. For inputs, this means that the external data is ignored, and internally the logic normally driven by a ...
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SYNTTXOUT CVBS HSYNC 10.2µs TTX DATA TTX DEL TTX REQ TTX 10.2µs. SYNTTXOUT t = PIPELINE DELAY THROUGH ADV7342/ADC7343. PD TTX = TTX TO TTX (PROGRAMMABLE RANGE = 4 BITS [ PIXEL ...
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ADV7342/ADV7343 PRINTED CIRCUIT BOARD LAYOUT AND DESIGN UNUSED PINS If the S_HSYNC , S_VSYNC , P_HSYNC , and P_VSYNC pins are not used, they should be tied to V through a pull-up resistor DD_IO (10 kΩ or 4.7 kΩ). Any ...
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DAC OUTPUT 3 390nH 75Ω 300Ω 1 33pF 33pF 75Ω 4 Figure 88. Example of Output Filter for HD, 4× Oversampling CIRCUIT FREQUENCY RESPONSE 0 –10 MAGNITUDE (dB) –20 –30 –40 –50 GROUP DELAY (Seconds) –60 –70 –80 1M 10M ...
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ADV7342/ADV7343 External filter and buffer components connected to the DAC outputs should be placed as close as possible to the ADV7342/ ADV7343 to minimize the possibility of noise pickup from neighboring circuitry and to minimize the effect of trace capacitance ...
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TYPICAL APPLICATION CIRCUIT FERRITE BEAD V DD_IO 33µF 10µF GND_IO GND_IO FERRITE BEAD PV DD (1.8V) 33µF 10µF PGND PGND FERRITE BEAD V AA 33µF 10µF AGND AGND FERRITE BEAD V DD (1.8V) 33µF 10µF DGND DGND ...
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ADV7342/ADV7343 COPY GENERATION MANAGEMENT SYSTEM SD CGMS Subaddress 0x99 to Subaddress 0x9B The ADV7342/ADV7343 support a copy generation management system (CGMS) conforming to the EIAJ CPR- 1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of odd ...
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IRE REF +70 IRE 0 IRE –40 IRE 11.2µs 2.235µs ± 20ns +700mV 70% ± 10% 0mV –300mV 5.8µs ± 0.15µs 6T Figure 94. Enhanced Definition (525p) CGMS Waveform PEAK WHITE R = RUN- START CODE 500mV ...
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ADV7342/ADV7343 +700mV 70% ± 10% 0mV –300mV 4T 4.15µs ± 60ns +700mV 70% ± 10% 0mV –300mV NOTES 1. PLEASE REFER TO THE CEA-805-A SPECIFICATION FOR TIMING INFORMATION. +700mV START 70% ± 10% 0mV –300mV NOTES 1. PLEASE REFER TO ...
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SD WIDE SCREEN SIGNALING Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B The ADV7342/ADV7343 support wide screen signaling (WSS) conforming to the ETSI 300 294 standard. WSS data is trans- mitted on Line 23. WSS data can be transmitted only when the ...
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ADV7342/ADV7343 SD CLOSED CAPTIONING Subaddress 0x91 to Subaddress 0x94 The ADV7342/ADV7343 support closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd ...
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INTERNAL TEST PATTERN GENERATION SD TEST PATTERNS The ADV7342/ADV7343 are able to internally generate SD color bar and black bar test patterns. For this function MHz clock signal must be applied to the CLKIN_A pin. The register settings ...
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ADV7342/ADV7343 SD TIMING Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = The ADV7342/ADV7343 are controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the ...
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DISPLAY 622 623 624 625 H F EVEN FIELD DISPLAY 309 310 311 312 H ODD FIELD F ANALOG VIDEO H F Mode 1—Slave Option (Subaddress 0x8A = this mode, the ...
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ADV7342/ADV7343 DISPLAY 622 623 624 625 HSYNC FIELD EVEN FIELD DISPLAY 309 310 311 312 HSYNC ODD FIELD FIELD Mode 1—Master Option (Subaddress 0x8A = this mode, the ADV7342/ADV7343 can generate ...
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DISPLAY 522 523 524 525 HSYNC VSYNC DISPLAY 260 261 262 263 HSYNC VSYNC DISPLAY 622 623 624 HSYNC VSYNC EVEN FIELD DISPLAY 309 310 311 HSYNC VSYNC ODD FIELD Mode 2—Master Option (Subaddress 0x8A = ...
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ADV7342/ADV7343 HSYNC VSYNC PIXEL DATA Figure 112. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave) Mode 3—Master/Slave Option (Subaddress 0x8A = this ...
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HD TIMING FIELD 1 1124 1125 P_VSYNC P_HSYNC FIELD 2 561 562 P_VSYNC P_HSYNC VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 115. 1080i HSYNC and VSYNC ...
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ADV7342/ADV7343 VIDEO OUTPUT LEVELS SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars 700mV 300mV Figure 116. Y Levels—NTSC 700mV Figure 117. Pr Levels—NTSC 700mV Figure 118. Pb Levels—NTSC 700mV 300mV Figure 119. Y Levels—PAL 700mV Figure 120. Pr Levels—PAL ...
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ED/HD YPrPb OUTPUT LEVELS EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 122. EIA-770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 EIA-770.1, STANDARD FOR Pr/Pb 960 512 ...
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ADV7342/ADV7343 SD/ED/HD RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars R 700mV/525mV 300mV G 700mV/525mV 300mV B 700mV/525mV 300mV Figure 126. SD/ED RGB Output Levels—RGB Sync Disabled R 700mV/525mV 300mV 0mV G 700mV/525mV 300mV 0mV B 700mV/525mV 300mV 0mV Figure 127. ...
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SD OUTPUT PLOTS VOLTS IRE:FLT 100 0 –50 L76 MICROSECONDS APL = 44.5% PRECISION MODE OFF 525 LINE NTSC SYNCHRONOUS SYNC = A SLOW CLAMP TO 0.00V AT 6.72μs µ FRAMES ...
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ADV7342/ADV7343 VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE INPUT PIXELS CLOCK SAMPLE NUMBER 2112 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125 ...
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ACTIVE VIDEO 622 623 624 625 Figure 139. ITU-R BT.1358 (625p) VERTICAL BLANKING INTERVAL 747 748 749 750 VERTICAL BLANKING INTERVAL FIELD 1 1124 1125 VERTICAL BLANKING INTERVAL FIELD 2 561 ...
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ADV7342/ADV7343 CONFIGURATION SCRIPTS The scripts listed in the following pages can be used to configure the ADV7342/ ADV7343 for basic operation. Certain features are enabled by default. If required for a specific application, additional features can be enabled. STANDARD DEFINITION ...
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Table 66. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb and CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0xFC All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x10 NTSC standard. SSAF luma filter enabled. 1.3 ...
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ADV7342/ADV7343 Table 73. 24-Bit 525i RGB In, RGB and CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0xFC All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. ...
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Table 80. 16-Bit 625i YCrCb In, YPrPb and CVBS/Y-C Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0xFC All DACs enabled. PLL enabled (16×). 0x01 0x00 SD input mode. 0x80 0x11 PAL standard. SSAF luma filter enabled. 1.3 MHz ...
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ADV7342/ADV7343 ENHANCED DEFINITION Table 86. ED Configuration Scripts 1 Input Format Input Data Width 525p at 59.94 Hz 8-bit DDR 525p at 59.94 Hz 8-bit DDR 525p at 59.94 Hz 8-bit DDR 525p at 59.94 Hz 16-bit SDR 525p at ...
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Table 91. 16-Bit 525p YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x30 0x00 525p at 59.94 Hz. HSYNC/VSYNC synch- ronization. EIA-770.2 output levels. ...
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ADV7342/ADV7343 Table 100. 8-Bit 625p YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x18 625p ...
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Table 110. 24-Bit 625p YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x18 625p ...
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ADV7342/ADV7343 Table 113. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x2C ...
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Table 121. 24-Bit 720p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x10 HD-SDR input mode. 0x30 0x2C 720p at 60 Hz/59.94 Hz. EAV/SAV syn- chronization. EIA-770.3 ...
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ADV7342/ADV7343 Table 129. 8-Bit 1080i YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB ...
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Table 137. 24-Bit 1080i YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x10 HD-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x68 1080i ...
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... VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 2 ADV7342BSTZ −40°C to +85°C 2 ADV7343BSTZ −40°C to +85°C 2 EVAL-ADV7342EBZ 2 EVAL-ADV7343EBZ 1 Macrovision-enabled ICs require the buyer approved licensee (authorized buyer) of ICs that are able to output Macrovision Rev 7.1.L1-compliant video RoHS Compliant Part. ...