ADV7343BSTZ Analog Devices Inc, ADV7343BSTZ Datasheet - Page 16

IC ENCODER VIDEO W/DAC 64-LQFP

ADV7343BSTZ

Manufacturer Part Number
ADV7343BSTZ
Description
IC ENCODER VIDEO W/DAC 64-LQFP
Manufacturer
Analog Devices Inc
Type
Video Encoderr
Datasheet

Specifications of ADV7343BSTZ

Applications
DVD, Blu-Ray
Voltage - Supply, Analog
3.3V
Voltage - Supply, Digital
1.8V
Mounting Type
Surface Mount
Package / Case
64-LQFP
Supply Voltage Range
1.71V To 1.89V
Operating Temperature Range
-40°C To +85°C
Tv / Video Case Style
LQFP
No. Of Pins
64
Svhc
No SVHC (18-Jun-2010)
Operating Temperature Max
85°C
Operating
RoHS Compliant
Input Format
Digital
Output Format
Analogue
Dac Resolution
11bit
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADV7343BSTZ
Manufacturer:
ADI
Quantity:
301
Part Number:
ADV7343BSTZ
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
ADV7343BSTZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
ADV7343BSTZ-3
Manufacturer:
ADI
Quantity:
246
Company:
Part Number:
ADV7343BSTZ-3
Quantity:
626
Company:
Part Number:
ADV7343BSTZ-3
Quantity:
320
ADV7342/ADV7343
P_HSYNC
P_VSYNC
P_BLANK
Y OUTPUT
a = 32 CLOCK CYCLES FOR 525p
a = 24 CLOCK CYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLOCK CYCLES FOR 525p
b(MIN) = 264 CLOCK CYCLES FOR 625p
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Y7 TO Y0
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMIN
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Y OUTPUT
P_HSYNC
P_BLANK
P_VSYNC
C7 TO C0
Y7 TO Y0
Figure 14. ED-SDR, 16-Bit, 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
Figure 15. ED-DDR, 8-Bit, 4:2:2 YCrCb ( HSYNC / VSYNC ) Input Timing Diagram
a
a
c
c
Rev. A | Page 16 of 104
b
b
Cb0
Y0
Cb0
Cr0
Y1
Y0
G
Cb2
Y2
Cr0
Cr2
Y3
Y1

Related parts for ADV7343BSTZ