MPC603RRX266TC Freescale Semiconductor, MPC603RRX266TC Datasheet - Page 9

• Manufacturer Part Number: MPC603RRX266TC
• Description: IC MPU 32BIT 266MHZ 255-CBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC603RRX266TC

• Processor Type: MPC603e PowerPC 32-Bit
• Speed: 266MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc , 0 £ Tj £ 105° C
10a
10b
10c
11a
11b
11c
Num
Note s:
1. Input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V of the rising edge
2. Address/data/transfer attribute input signals are composed of the following—A[0–31], AP[0–3], TT[0–4], TC[0–1], TBST,
3. All other input signals are composed of the following—TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY,
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3).
5. t
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode only. Also note that HRESET must be held asserted for a minimum of 255
Figure 1 provides the SYSCLK input timing diagram.
1.4.2.2 Input AC SpeciÞcations
Table 8 provides the input AC timing speciÞcations for the PID7t-603e as deÞned in Figure 2 and Figure 3.
SYSCLK
of the input SYSCLK. Input and output timings are measured at the pin.
TSIZ[0–2], GBL, DH[0–31], DL[0–31], DP[0–7].
TEA, DBDIS, HRESET, SRESET, INT, SMI, MCP, TBEN, QACK, TLBISYNC.
multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
bus clocks after the PLL-relock time during the power-on reset sequence.
sysclk
Address/data/transfer attribute inputs valid to SYSCLK (input setup)
All other inputs valid to SYSCLK (input setup)
Mode select inputs valid to HRESET (input setup)
(for DRTRY, QACK and TLBISYNC)
SYSCLK to address/data/transfer attribute inputs invalid (input hold)
SYSCLK to all other inputs invalid (input hold)
HRESET to mode select inputs invalid (input hold)
(for DRTRY, QACK, and TLBISYNC)
is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be
VM
4
Characteristic
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 1. SYSCLK Input Timing Diagram
Table 8. Input AC Timing Specifications
1
PID7t-603e Hardware Specifications
VM
VM = Midpoint Voltage (1.4 V)
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4
VM
CVil
Electrical and Thermal Characteristics
CVih
200, 266, 300 MHz
Min
2.5
3.5
1.0
1.0
8
0
1
Max
—
—
—
—
—
—
2
t
Unit
sysclk
ns
ns
ns
ns
ns
3
2
3
4, 5, 6, 7
2
3
4, 6, 7
Notes
9