MPC603RRX266TC Freescale Semiconductor, MPC603RRX266TC Datasheet - Page 8

• Manufacturer Part Number: MPC603RRX266TC
• Description: IC MPU 32BIT 266MHZ 255-CBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC603RRX266TC

• Processor Type: MPC603e PowerPC 32-Bit
• Speed: 266MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

1.4.2.1 Clock AC SpeciÞcations
Table 7 provides the clock AC timing speciÞcations as deÞned in Figure 1. After fabrication, parts are sorted
by maximum processor core frequency as shown in Section 1.4.2.1, ÒClock AC SpeciÞcations,Ó and tested
for conformance to the AC speciÞcations for that frequency. Parts are sold by maximum processor core
frequency; see Section 1.9, ÒOrdering Information.Ó
Electrical and Thermal Characteristics
8
1
2,3
4
Vdd = AVdd = 2.5 ± 5% V dc, OVdd = 3.3 ± 5% V dc, GND = 0 V dc , 0 £ Tj £ 105 °C
Num
Notes :
1. Caution : The SYSCLK frequency and PLL_CFG[0–3] settings must be chosen such that the resulting
2. Rise and fall times for the SYSCLK input are measured from 0.4 V to 2.4 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. Cycle-to-cycle jitter, and is guaranteed by design. The total input jitter (short term and long term
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the
6. Operation below 150 MHz is supported only by PLL_CFG[0–3] = 0b0101. Refer to Section 1.8.1, “PLL
SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their
respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0–3] signal description
in Section 1.8, “System Design Information,” for valid PLL_CFG[0–3] settings.
combined) must be under ±150 ps to guarantee the input/output timing of Section 1.4.2.2, “Input AC
Specifications,” and Section 1.4.2.3, “Output AC Specifications.”
maximum time required for PLL lock after a stable Vdd, OVdd, AVdd, and SYSCLK are reached during
the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a
minimum of 255 bus clocks after the PLL-relock time (100 m s) during the power-on reset sequence.
Configuration” for additional information.
Processor
frequency
VCO
frequency
SYSCLK
frequency
SYSCLK
cycle time
SYSCLK rise
and fall time
SYSCLK duty
cycle measured at
1.4 V
SYSCLK jitter
PID7t internal
PLL-relock time
Characteristic
100
300
25
13.3
—
40.0
—
—
Min
Freescale Semiconductor, Inc.
200 MHz
PBGA
For More Information On This Product,
Table 7. Clock AC Timing Specifications
200
400
66.67
40
2.0
60.0
±150
100
PID7t-603e Hardware Specifications
Max
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80
300
25
13.3
—
40.0
—
—
Min
200 MHz
CBGA
200
400
66.67
40
2.0
60.0
±150
100
Max
150
300
25
13.3
—
40.0
—
—
Min
266 MHz
CBGA
266
532
75
40
2.0
60.0
±150
100
Max
180
360
33.3
13.3
—
40.0
—
—
Min
300 MHz
CBGA
300
600
75
30
2.0
60.0
100
±150
Max
MHz
MHz
MHz
ns
ns
%
m s
ps
Unit
1,6
1
1
2
3
3,5
Notes
4