MPC603RRX266TC Freescale Semiconductor, MPC603RRX266TC Datasheet - Page 24

• Manufacturer Part Number: MPC603RRX266TC
• Description: IC MPU 32BIT 266MHZ 255-CBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC603RRX266TC

• Processor Type: MPC603e PowerPC 32-Bit
• Speed: 266MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 255-CBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

1.8.2 PLL Power Supply Filtering
The AVdd power signal is provided on the 603e to provide power to the clock generation phase-locked loop.
To ensure stability of the internal clock, the power supplied to the AVdd input signal should be Þltered using
a circuit similar to the one shown in Figure 13. The circuit should be placed as close as possible to the AVdd
pin to ensure it Þlters out as much noise as possible. The 0.1 µF capacitor should be closest to the AVdd pin,
followed by the 10 µF capacitor, and Þnally the 10 W resistor to Vdd. These traces should be kept short and
direct.
1.8.3 Decoupling Recommendations
Due to the 603eÕs dynamic power management feature, large address and data buses, and high operating
frequencies, the 603e can generate transient power surges and high frequency noise in its power supply,
especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the 603e system, and the 603e itself requires a clean, tightly regulated source of power.
Therefore, it is recommended that the system designer place at least one decoupling capacitor at each Vdd
and OVdd pin of the 603e. It is also recommended that these decoupling capacitors receive their power from
separate Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should vary in value from 220 pF to 10 mF to provide both high- and low-frequency
Þltering, and should be placed as close as possible to their associated Vdd or OVdd pin. Suggested values
for the Vdd pinsÑ220 pF (ceramic), 0.01 µF (ceramic), and 0.1 µF (ceramic). Suggested values for the
OVdd pinsÑ0.01 µF (ceramic), 0.1 µF (ceramic), and 10 µF (tantalum). Only SMT (surface mount
technology) capacitors should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk
capacitors should also have a low ESR (equivalent series resistance) rating to ensure the quick response time
necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitorsÑ100 µF (AVX TPS tantalum) or 330 µF (AVX TPS tantalum).
1.8.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the 603e.
System Design Information
24
Vdd
Freescale Semiconductor, Inc.
Figure 13. PLL Power Supply Filter Circuit
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PID7t-603e Hardware Specifications
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10 µF
GND
0
.
1 µF
AVdd