GCIXP1250BC 837414 Intel, GCIXP1250BC 837414 Datasheet - Page 67

• Manufacturer Part Number: GCIXP1250BC 837414
• Manufacturer: Intel

Specifications of GCIXP1250BC 837414

• Lead Free Status / Rohs Status: Supplier Unconfirmed

3.9
Datasheet
Table 30. Pin State During Reset (Continued)
Pullup/Pulldown and Unused Pin Guidelines
For normal (i.e., non-test mode) operation, terminate signals as follows:
Terminate unused signals as follows:
For shared IX Bus operation, it is recommended to pullup PORTCTL_L[3:0] and, additionally,
FPS[2:0] and TXAXIS at the designer’s discretion.
Typical pullup/pulldown resistor values are in the range of 5-10 KOhms.
Misc Test
Misc Test
Processor
Support
Processor
Support
Processor
Support
Processor
Support
Serial
Serial
IEEE 1149.1
IEEE 1149.1
IEEE 1149.1
IEEE 1149.1
IEEE 1149.1
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•
•
•
•
•
•
Function
Pullup these signals to VDDX: TMS, TDI.
TCK may be pulled up toVDDX or down to VSSX at the system designer’s option.
Pulldown these signals to VSS: SCAN_EN, TCK_BYP, TRST_L.
Pullup this signal to VDDX or pulldown to VSS; do not allow it to float: TSTCLK.
GPIO[3:1] and GPIO[0] are tri-stated during reset. If these signals are used to drive external
logic, pullup or pulldown as approprate to ensure valid logic levels during reset.
Pullup these signals to VDDX: GNT_L[1], TK_IN, EOP32.
Pulldown these signals to VSS: NA/SACLK, FAST_RX1, FAST_RX2.
TSTCLK
SCAN_EN
PXTAL
CINT_L
RESET_IN_L
RESET_OUT_L
RXD
TXD
TCK
TDI
TDO
TMS
TRST_L
Pin Name
input
input
input
input
input
output, low
input
output, high
input
input
output, undefined
input
input
Pin Reset State
Intel
®
IXP1250 Network Processor
Comment
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