GCIXP1250BC 837414 Intel, GCIXP1250BC 837414 Datasheet - Page 18

• Manufacturer Part Number: GCIXP1250BC 837414
• Manufacturer: Intel

Specifications of GCIXP1250BC 837414

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
2.5.5
2.5.6
18
Table 6.
®
IXP1250 Network Processor
If the codes match, the data is free of errors and is sent.
If the codes don’t match, the missing or erroneous bits are determined through the code comparison
and the bit or bits are supplied or corrected.
ECC only corrects single bit errors. Multiple bit errors are detected, but not corrected.
No hardware attempt is made to correct the data that is still in storage. Eventually, it will be
overlaid by new data and, assuming the errors were transient, the incorrect bits will "go away."
There are no timing penalties associated with ECC operation.
SDRAM Configurations
SDRAM Configurations
SRAM Unit
The IXP1250 provides an SRAM Unit for very high bandwidth memory for storage of lookup
tables and other data for the packet processing Microengines. The SRAM Unit controls the SRAM
(up to 8 Mbytes), BootROM (up to 8 Mbytes) for booting, and 2 Mbytes of SlowPort address space
for peripheral device access. The I/O signal timing is determined by internal address decodes and
configuration registers for the BootROM and SlowPort address regions. The SRAM Unit includes
an 8 entry Push/Pop register list for fast queue operations, bit test, set and clear instructions for
atomic bit operations, and an 8 entry CAM for Read Locks.
The SRAM interface operates at one-half the IXP1250 Core frequency (0.5 * F
The SRAM Unit supports both Pipelined Burst Double Cycle Deselect (DCD) and Flowthru
SRAM types. Other SSRAM devices, including single cycle deselect, are not supported. The bus is
also used to attach BootROM and can be used to interface other peripheral devices such as custom
interface logic or MAC management ports. The SRAM interface provides three separate timing
domains for the three device types: SRAM, BootROM, and Peripheral (also referred to as SlowPort
access).
128 Mbytes
128 Mbytes
256 Mbytes
16 Mbytes
32 Mbytes
64 Mbytes
32 Mbytes
64 Mbytes
64 Mbytes
8 Mbytes
Memory
Total
Number of
Chips
4
8
4
8
4
8
4
8
4
8
128 Mbit
128 Mbit
256 Mbit
256 Mbit
16 Mbit
16 Mbit
64 Mbit
64 Mbit
64 Mbit
64 Mbit
DRAM
Size
Configuration
512 K x 16-bit
2 M x 16-bit
1 M x 16-bit
2 M x 16-bit
4 M x 16-bit
(per bank)
1 M x 8-bit
4 M x 8-bit
2 M x 8-bit
4 M x 8-bit
8 M x 8-bit
Internal
Banks
2
2
2
2
4
4
4
4
4
4
Bank Bits
1
1
1
2
2
2
2
1
2
2
RAS Bits
core
13
13
12
12
12
12
13
13
11
11
).
Datasheet
CAS Bits
10
10
8
9
8
9
8
9
9
9