GCIXP1250BC 837414 Intel, GCIXP1250BC 837414 Datasheet - Page 137

• Manufacturer Part Number: GCIXP1250BC 837414
• Manufacturer: Intel

Specifications of GCIXP1250BC 837414

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.3.9.2
Datasheet
Figure 76. SDRAM Bus Signal Timing
Table 51. SDRAM Bus Signal Timing Parameters
SDRAM Bus Signal Timing
1. Timing parameters assume that the system uses a zero delay clock buffer for SDCLK before it is distributed to SDRAM.
2. Capacitive loading effects on signal lines are shown in
3. T
4. Unlike the SRAM setup timing parameterT
5. Not tested. Guaranteed by design.
Symbol
T
T
T
T
T
T
ctl
su
on
off
val
h
SDRAM parts will deliver. Increased performance on the SDRAM bus occurs because the data pins only drive one load.
Vddx=3.6, Temp=0 degrees C) at 1.15 nsec with an uncertainty of 0.25 nsec. The parameter specified is guaranteed by design
in a minimally configured system environment.
5
5
val
(min) and 166 MHz and 200 MHz T
MDATA_ECC (output)
WE_L, DQM, MADR)
MDATA_ECC (input)
Clock to data output valid delay
SDCLK to control output valid delay
Data input setup time before SDCLK
Data input hold time from SDCLK
Float to data driven delay from SDCLK
Data driven to float delay from SDCLK
(RAS_L, CAS_L,
Control Outputs
MDATA (output)
MDATA (input)
SDCLK
Parameter
ctl
(min) parameters are tested under 0 pF load best case conditions (Vdd=2.1,
sup
, the T
2,3
T
T
on
val(max)
2,3
4
su
timings are both what the tester must measure and what the
Table
1
1.25
1.25
4.25
1
1.25
---
MHz
166
T
52.
ctl(max)
(IXP1250 Core
Minimum
Speed)
1.0
1.0
3.70
1
1
---
T
MHz
200
su
Intel
0.5
0.5
3.70
0.75
0.75
---
®
MHz
232
IXP1250 Network Processor
T
h
T
off
---
---
---
4.5
4.5
3
MHz
166
(IXP1250 Core
T
T
val(min)
ctl(min)
Maximum
Speed)
4.0
4.0
---
---
---
3
MHz
200
3.3
2.90
---
---
---
3
MHz
232
A8623-01
ns
ns
ns
ns
ns
ns
Unit
137