GCIXP1250BC 837414 Intel, GCIXP1250BC 837414 Datasheet

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... Dual DMA channels Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Datasheet Industry Standard 64-bit SDRAM Interface — ...

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... Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...

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... IEEE 1149.1 Interface Pins ....................................................................42 3.3.10 Miscellaneous Test Pins.........................................................................42 3.3.11 Pin Usage Summary ..............................................................................43 3.4 Pin/Signal List......................................................................................................44 3.5 Signals Listed in Alphabetical Order ...................................................................49 3.6 IX Bus Pins Function Listed by Operating Mode.................................................53 3.7 IX Bus Decode Table Listed by Operating Mode Type .......................................63 Datasheet ® Intel IXP1250 Network Processor iii ...

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... Intel IXP1250 Network Processor 3.8 Pin State During Reset........................................................................................ 65 3.9 Pullup/Pulldown and Unused Pin Guidelines ...................................................... 67 4.0 Electrical Specifications ................................................................................................... 68 4.1 Absolute Maximum Ratings ................................................................................ 68 4.2 DC Specifications................................................................................................ 71 4.2.1 Type 1 Driver DC Specifications ............................................................ 71 4.2.2 Type 2 Driver DC Specifications ............................................................ 72 4.2.3 Overshoot/Undershoot Specifications .................................................... 72 4.3 AC Specifications ................................................................................................ 73 4.3.1 Clock Timing Specifications ................................................................... 73 4 ...

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... EOP...................................................................................................................100 38 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, No EOP.............101 39 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 16th Data Return with Status ....................................................................................102 40 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 15th Data Return with Status ....................................................................................103 Datasheet ® Intel IXP1250 Network Processor v ...

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... Intel IXP1250 Network Processor 41 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 14th Data Return with Status ............................................................................ 104 42 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP on 1st Through 13th Data Return with Status (13th Data Return Shown) ................... 105 43 32-Bit Unidirectional IX Bus Timing - Consecutive Receives, EOP, 64-Bit Status ...

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... Unidirectional IX Bus, 1-2 MAC Mode ......................................................60 28 32-bit Unidirectional IX Bus, 3+ MAC Mode ........................................................ Bus Decode Table Listed by Operating Mode Type .......................................63 30 Pin State During Reset........................................................................................65 31 Absolute Maximum Ratings.................................................................................68 32 Functional Operating Range ...............................................................................69 33 Typical and Maximum Power ..............................................................................69 Datasheet ® Intel IXP1250 Network Processor vii ...

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... Intel IXP1250 Network Processor 34 Maximum and Typical Bus Loading Used for the Power Calculations................ 70 35 I1, I3, O1, O3, O4, and O5 Pin Types ................................................................. and O2 Pin Types ........................................................................................... 72 37 Overshoot/Undershoot Specifications................................................................. 72 38 PXTAL Clock Inputs ............................................................................................ MHz PCI Clock Signal AC Parameters .......................................................... MHz PCI Clock Signal AC Parameters .......................................................... MHz PCI Signal Timing ...

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... GPIO RTC SRAM Unit Micro- engine 1 FBI Unit Scratchpad Memory (4 Kbyte) Hash Unit IX Bus Interface Micro- engine 4 Intel IXP1250 Network Processor ® Intel IXP1250 Network Processor PCI Unit 32-bit bus 64-bit bus SDRAM Unit Micro- Micro- engine engine 2 3 Micro- Micro- ...

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... Figure 2. System Block Diagram SSRAM (8 Mbytes Max) Buffer BootROM (8 Mbytes Max) SlowPort Devices (2 Mbytes Max PCI Bus (33-66Mhz) 32 Control ® Intel Data 32 IXP1250 r Processo 64 IX Bus Data Control and Status Network Interface Devices Network Command SDRAM (256 Mbytes 64 Data Max) JTAG ...

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... Architecture Reference typically refer to a word as being equal to 32 bits, and a halfword as being equal to 16 bits. 2.2 StrongARM* Core Microprocessor The StrongARM* core is the same industry standard 32-bit RISC processor as used in the Intel * StrongARM SA-1100 compatible with the StrongARM* processor family currently used in applications such as network computers, PDAs, palmtop computers and portable telephones ...

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... Intel IXP1250 Network Processor 2.4 FBI Unit and the IX Bus The FBI Unit is responsible for servicing fast peripherals, such as MAC-layer devices, on the IX Bus. This includes moving data to and from the IXP1250 Receive and Transmit FIFOs. The IX Bus provides a 4.4 Gbps interface to peripheral devices. The IX Bus was specifically designed to provide a simple and efficient interface ...

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... Table 26 tri-state. The IX Bus and Intel devices using the IX Bus, such as the IXF440 and IXF1002, observe a pipelined bus protocol. When receive transfers are terminated early, the pipeline continues to cause several extra bus cycles depending on when the EOP signal was asserted. Data is a “don't care” for these trailing bus cycles, except in the case of a status transfer where the IX Bus burst includes a possible status transfer if the device were programmed to support it ...

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... Intel IXP1250 Network Processor Table 4. 32-bit IX Bus Receive Remainder Cycles, with Status Transfer EOP signaled on this cycle: Number of bus cycles in burst: 32-bit status Status transfer 64-bit status Number of Don’t Care cycles: NOTE: 1. Status transfer occurs on one or two subsequent IX Bus cycles. ...

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... Transmit and Receive FIFOs in the FBI Unit. Refer to the IXP1200 Network Processor Family Hardware Reference Manual for details on how these requests are queued, prioritized, and serviced by the SDRAM Unit. SDRAM should have an access time (t Datasheet ® Intel IXP1250 Network Processor ) less (CAS latency = 2), PC100 compatible providing a peak core ...

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... Intel IXP1250 Network Processor Figure 3 details the major components of the SDRAM Unit. Figure 3. SDRAM Unit Block Diagram WE_L,RAS_L CAS_L, DQM SDRAM up to Addr[14:0] 256 MB Data[63:0] SDCLK MDATA_ECC[7:0] * Other names and brands may be claimed as the property of others. ** ARM architecture compatible The SDRAM Bus consists of 15 row/column address bits, 64 data bits, RAS_L, CAS_L, write enable, DQM control, and a synchronous output clock running at one-half the IXP1250 Core frequency (0 ...

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... The newly generated code is compared with the code generated when the word was stored. Datasheet Table 5. Polynomial +X +x+1 ® Intel IXP1250 Network Processor Application Bit Order 10 8 ATM AAL5 MSB first +X Ethernet LSB first HDLC LSB first Frame Relay LSB first MSB first, ATM OAM LW (or LW +1) 17 ...

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... Intel IXP1250 Network Processor If the codes match, the data is free of errors and is sent. If the codes don’t match, the missing or erroneous bits are determined through the code comparison and the bit or bits are supplied or corrected. ECC only corrects single bit errors. Multiple bit errors are detected, but not corrected. ...

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... Pause State Value field located in register SRAM_SLOW_CONFIG[23:16] must be programmed with the state value at which you choose to pause the internal wait-state logic. This pause state relates to the other timing parameters programmed into the SRAM_SLOW_CONFIG and Datasheet ® Intel IXP1250 Network Processor Service Priority (Arbitration) Machine & Registers ...

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... Intel IXP1250 Network Processor SRAM_SLOWPORT_CONFIG register fields. See SCC value is the total number of Core clocks for the I/O cycle, and the SRWA, SCEA, SRWD, and SCED values specify the RD/WR and Chip Enable signal assert and deassert times. When the I/O cycles begins, the SCC value is loaded into the internal state counter and is decremented on each Core clock tick (twice the SCLK frequency) ...

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... I/O device coherency. — For best performance, use longword accesses to avoid Read-Modify-Write cycles on the SRAM Bus that occur with byte and word accesses. • Accesses from the Microengines: Datasheet ® Intel Number of Chips Size of Boot ROM (Maximum Mbit 8 ...

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... PCI devices are supported only, the IXP1250 and a second PCI device. To increase the number of PCI devices supported or to add connectors to the bus at the higher PCI Bus speeds, a PCI-to-PCI bridge device, such the Intel 21150, 21152, or 21153 is required. Both PCI Initiator and Target cycles are supported target device, the IXP1250 responds as a Medium Speed device asserting DEVSEL_L two PCI_CLK cycles after FRAME_L is asserted ...

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... Hardware Reset via RESET_IN_L pin • Software Reset by StrongARM* core or by PCI device write to the IXP1250_RESET register • PCI Reset via the PCI_RST_L pin • Watchdog Timer expiration Figure 5 illustrates details of the internal reset function logic. Datasheet ® Intel IXP1250 Network Processor PCI FUNCTION 23 ...

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Output Pin RESET_OUT_L ext_rst Soft reset timer rst_in_sync start !zero 140 cycle counter Core clock [31] [30] [29] [28:19] [18] [17] cmd SA PCI sram sdram res arb Core reset reset reset reset reset reset Internal Reset Signals strongarm_rst pci_rst ...

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... If the watchdog timer expires assumed the StrongARM* core has ceased executing instructions properly. The reset generated by the Watchdog Timer will reset each of the functions in the IXP1250. Datasheet ® Intel IXP1250 Network Processor 25 ...

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... Intel IXP1250 Network Processor 3.0 Signal Description 3.1 Pinout Diagram Figure 6. Pinout Diagram Processor Support Miscellaneous Test IEEE 1149.1 SRAM Interface MDATA_ECC[7:0] SDRAM Interface Power Supply 26 RESET_OUT_L RESET_IN_L PXTAL CINT_L SCAN_EN TCK_BYP TSTCLK TCK TMS IXP1250 TDI TDO TRST_L NA/SACLK ...

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... P Power supply. Standard open drain allows multiple devices to share as a wire-OR. A pullup is required to OD sustain the inactive state until another agent drives it, and it must be provided by the central resource. Datasheet Intel Description and Table 36 for more information. and Table 36 for more information. ...

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... Intel IXP1250 Network Processor 3.3 Pin Description, Grouped by Function 3.3.1 Processor Support Pins Table 12. Processor Support Pins Processor Support Signal Names PXTAL CINT_L RESET_OUT_L RESET_IN_L Totals: 28 Pin Type Total Number Input connection for system oscillator. Typically 3.6864 MHz. Drives internal PLL clock generator. ...

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... K28 K29 K31 L28 L29 L30 M27 M28 M29 M30 M31 N27 N28 N29 32 32 Bidirectional data signals N30 N31 P27 P28 P29 P30 P31 R27 R28 R29 R30 U31 V30 V29 V28 V27 ® Intel IXP1250 Network Processor Pin Descriptions 29 ...

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... Intel IXP1250 Network Processor Table 13. SRAM Interface Pins (Continued) SRAM Interface Signal Names CE_L[3:0] [3] [2] [1] [0] SCLK SOE_L SWE_L LOW_EN_L HIGH_EN_L SLOW_EN_L NA/SACLK FWE_L MRD_L MCE_L Totals: 30 Pin Type Total Number SRAM Bus chip enable outputs. Internally decoded from D24 ...

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... AD3 [45] V4 [44] V3 [43] R3 [42] R4 [41] R5 [40] P1 [39] P2 [38] P3 [37] P4 [36] P5 [35] N1 [34] N2 [33] N3 [32] N4 [31] N5 [30] M1 [29] M2 [28] M3 [27] M4 [26] M5 Datasheet Pin Type Total O4 15 Multiplexed Row/Column address outputs. I1/ Bidirectional data signals. ® Intel IXP1250 Network Processor Pin Descriptions 31 ...

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... Intel IXP1250 Network Processor Table 14. SDRAM Interface Pins (Continued) SDRAM Interface Number Signal Names [25] L2 [24] L3 [23] L4 [22] K2 [21] K3 [20] K5 [19] J2 [18] J3 [17] J4 [16] H1 [15] J5 [14] H2 [13] H3 [12] H4 [11] G1 [10] H5 [9] G2 [8] G3 [7] G4 [6] F2 [5] G5 [4] F3 [3] E1 [2] F4 [1] E2 [0] F5 ...

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... Two 32-bit buses in unidirectional IX Bus mode where bits I2/O5/ 64 [63:32] are used for Transmit Data output and [31:0] are TS used for Receive Data input shared IX Bus system, these pins will be tri-stated when passing ownership of the IX Bus. ® Intel IXP1250 Network Processor Pin Descriptions 33 ...

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... Intel IXP1250 Network Processor Table 15. IX Bus Interface Pins (Continued) IX Bus Signal Names Number [30] AK22 [29] AH21 [28] AJ21 [27] AK21 [26] AG20 [25] AH20 [24] AJ20 [23] AK20 [22] AL20 [21] AG19 [20] AH19 [19] AJ19 [18] AK19 [17] AL19 [16] AG18 [15] AH18 [14] AJ18 [13] AK18 [12] AL18 [11] AG17 [10] AH17 [9] AJ17 [8] AK17 [7] AL15 [6] AK15 [5] AJ15 ...

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... Input/Output in 64-bit bidirectional IX Bus mode. SOP is I1/TS 1 Transmit Start of Packet output according to values programmed in the TFIFO control field. Is Receive Start of Packet input during receive cycles. • shared IX Bus system, this pin will be tri-stated when passing ownership of the IX Bus. ® Intel IXP1250 Network Processor Pin Descriptions 35 ...

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... Intel IXP1250 Network Processor Table 15. IX Bus Interface Pins (Continued) IX Bus Signal Names Number EOP AJ12 EOP32 AL7 SOP32 AH8 TK_OUT AA29 TK_IN AA28 Totals: 36 Pin Type Total End of Packet Indication. • Receive End of Packet Input in 32-bit unidirectional IX Bus mode. ...

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... MAC 64-bit Bidirectional IX Bus mode: Accessible to the I1/O4 1 StrongARM* core. Configurable as input or output. 3+ MAC 32-bit Unidirectional IX Bus mode: Active high Transmit Port Enable for an external PORTCTL_L[3:2] decoder. 4 Pin Type Total I1 1 UART Receive data UART Transmit data. 2 ® Intel IXP1250 Network Processor Pin Descriptions Pin Descriptions 37 ...

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... Intel IXP1250 Network Processor 3.3.7 PCI Interface Pins Table 18. PCI Interface Pins PCI Interface Signal Names Number AD[31:0] [31] D19 [30] C19 [29] B19 [28] D18 [27] C18 [26] B18 [25] A18 [24] E17 [23] B17 [22] A17 [21] B15 [20] C15 [19] D15 [18] E15 [17] A14 [16] B14 [15] C12 [14] D12 [13] E12 [12] B11 [11] C11 [10] ...

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... PCI_RST_L is an input, and when asserted resets the IXP1250 StrongARM* core, all registers, all transaction queues, and all PCI related state. PCI Clock input. Reference for PCI signals and internal I2 1 operations. PCI clock is typically MHz. ® Intel IXP1250 Network Processor Pin Descriptions 39 ...

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... Intel IXP1250 Network Processor Table 18. PCI Interface Pins (Continued) PCI Interface Signal Names Number PCI_CFN [1] A23 [0] E22 GNT_L[0] C20 REQ_L[0] B20 GNT_L[1] A20 REQ_L[1] E19 Totals: 40 Pin Type Total PCI Central Function and arbitration select inputs. Sampled on the rising edge of RESET_IN_L. ...

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... IXP1250 I/O supply (3.3V). 68 IXP1250 3.3V reference - used to bias the ESD circuitry Can tied directly to VDDX external to chip IXP1250 PLL ground. IXP1250 2V PLL supply. Use decoupling capacitor between P 1 VDDP1 and VSSP1 IXP1250 ground. 73 168 ® Intel IXP1250 Network Processor Pin Descriptions 41 ...

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... Used for Intel test purposes only. When high, bypasses I1 1 PLL for Test/debug. Must be low for normal system operation. Used for Intel test purposes only. Used as clock input when bypassing the internal PLL clock generator. For I1 1 Normal operation, this pin should not be allowed to float. ...

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... Pin Usage Summary Table 22. Pin Usage Summary Type Inputs Outputs Bidirectional Total Signal Power Overall Totals: Datasheet ® Intel IXP1250 Network Processor Quantity 21 68 235 324 168 520 43 ...

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... Intel IXP1250 Network Processor 3.4 Pin/Signal List Table 23. Pin Table in Pin Order Pin Signal Name Number A1 VSS A2 VSS A3 VSS A4 VSS A5 UNUSED22 A6 VSS A7 VSS A8 AD[2] A9 AD[7] A10 AD[9] A11 VSS A12 PAR A13 TRDY_L A14 AD[17] A15 VDDX A16 VSS A17 ...

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... VDD_REF E4 VDDX E5 VDDX E6 UNUSED25 E7 PXTAL E8 RESET_OUT_L E9 AD[1] E10 AD[6] E11 VDDX E12 AD[13] E13 SERR_L Datasheet ® Intel IXP1250 Network Processor Pin Signal Name Number Number E14 IRDY_L G29 E15 AD[18] G30 E16 VDDX G31 E17 AD[24] H1 E18 VDD H2 E19 REQ_L[1] ...

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... Intel IXP1250 Network Processor Table 23. Pin Table in Pin Order (Continued) Pin Signal Name Number L3 MDATA[24] L4 MDATA[23] L5 VDDX L27 VDDX L28 DQ[26] L29 DQ[25] L30 DQ[24] L31 VSS M1 MDATA[30] M2 MDATA[29] M3 MDATA[28] M4 MDATA[[27] M5 MDATA[26] M27 DQ[23] M28 DQ[22] M29 DQ[21] M30 ...

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... MDATA[47] AD5 MDATA[49] AD27 VDD AD28 FDAT[60] AD29 FDAT[61] AD30 FDAT[62] AD31 FPS[0] AE1 MDATA[48] AE2 MDATA[50] Datasheet ® Intel IXP1250 Network Processor Pin Signal Name Number Number AE3 MDATA[51] AG18 AE4 MDATA[52] AG19 AE5 MDATA[54] AG20 AE27 FDAT[55] AG21 AE28 ...

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... Intel IXP1250 Network Processor Table 23. Pin Table in Pin Order (Continued) Pin Signal Name Number AH22 FDAT[32] AH23 FDAT[37] AH24 FDAT[42] AH25 FDAT[47] AH26 UNUSED6 AH27 VDDX AH28 VDDX AH29 VDDX AH30 VDDX AH31 VSS AJ1 VSS AJ2 VSS AJ3 VDDX ...

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... A[6] A[7] A[8] A[9] AD[0] AD[1] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[2] AD[20] AD[21] Datasheet Intel Pin Pin Signal Name Number Number H31 AD[22] A17 J27 AD[23] B17 F30 AD[24] E17 G27 AD[25] A18 F29 AD[26] ...

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... Intel IXP1250 Network Processor Table 24. Pin Table in Alphabetical Order (Continued) Signal Name FBE_L[3] FBE_L[4] FBE_L[5] FBE_L[6] FBE_L[7] FCLK FDAT[0] FDAT[1] FDAT[10] FDAT[11] FDAT[12] FDAT[13] FDAT[14] FDAT[15] FDAT[16] FDAT[17] FDAT[18] FDAT[19] FDAT[2] FDAT[20] FDAT[21] FDAT[22] FDAT[23] FDAT[24] FDAT[25] FDAT[26] FDAT[27] FDAT[28] ...

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... MDATA[31] MDATA[32] MDATA[33] MDATA[34] MDATA[35] MDATA[36] MDATA[37] MDATA[38] MDATA[39] MDATA[4] MDATA[40] MDATA[41] MDATA[42] MDATA[43] MDATA[44] MDATA[45] MDATA[46] MDATA[47] MDATA[48] MDATA[49] MDATA[5] MDATA[50] Datasheet Intel Pin Pin Signal Name Number Number J3 MDATA[51] AE3 J2 MDATA[52] AE4 F4 MDATA[53] AF2 K5 MDATA[54] AE5 K3 MDATA[55] AF3 K2 MDATA[56] ...

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... Intel IXP1250 Network Processor Table 24. Pin Table in Alphabetical Order (Continued) Signal Name TK_OUT TMS TRDY_L TRST_L TSTCLK TXASIS TXD WE_L VDD VDDX VDD_REF VDD_P1 VSS VSSP1 UNUSED0 - UNUSED26 (not listed in order) 52 Pin Pin Signal Name Number Number AA29 B22 A13 ...

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... CINT_L GPIO[3:1] not used GPIO[0] RDYBUS[7:0] RDYCTL_L[4:0] [0] [2] FPS[2:0] FDAT[63:0] FBE_L[7:0] SOP EOP TXAXIS RxFAIL SOP32 not used EOP32 3.3V [1] [3] ® Intel IXP1250 Network Processor 3.3V MAC0 wireor CINT[7: FLCTL[7:0] e FCLK RxRDY[7:0] TxRDY[7:0] [0] RxCTL_L [1] TxCTL_L RxSEL_L TxSEL_L FPS[2:0] FDAT[63:0] FBE_L[7:0] ...

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... FAST_RX2 [0] PORTCTL_L[3:0] [2] [0] FPS[2:0] FDAT[63:0] FBE_L[7:0] SOP EOP TXAXIS RxFAIL 3.3V SOP32 not used EOP32 Dual Fast Port Device CINT_L[1:0] ® (Intel IXF1002) [1:0] FLCT[1:0] FLCT_LAT [1:0] TxRDY[1:0] TxCTL_L RxRDY[1:0] RxCTL_L RxSEL_L TxSEL_L FPS FDAT[63:0] FBE_L[7:0] SOP EOP TXAXIS RxFAIL RxKEP ...

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... FBE_L[7:0] FDAT[63:0] FAST_RX1 FAST_RX2 Datasheet Intel Description Active High, input/output assigned to StrongARM* core not used for MAC interface. Active Low, output flow-control enable for MAC 0. Active Low, output, enables for Transmit or Receive Ready flags. Active Low, output, flow-control enable for MAC 1. ...

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... Intel IXP1250 Network Processor Figure 9. 64-Bit Bidirectional IX Bus, 3+ MAC Mode ® Intel IXP1250 Processor 56 CINT_L GPIO[3:0] not used RDYBUS[7:0] [31:0] RDYCTL_L[4:0] 5 > 32 FCLK [15:0] PORTCTL_L[3:0] 4 > 16 FCLK FPS[2:0] FDAT[63:0] FBE_L[7:0] SOP EOP TXAXIS RxFAIL not used SOP32 EOP32 3.3V 3.3V ...

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... RXFAIL TXASIS FBE_L[7:0] FDAT[63:0] Datasheet Intel Description Active High input/output assigned to StrongARM* core not used for MAC interface. Active High, output assigned to StrongARM* core not used for MAC interface. Output, 5 bits encoded for Transmit/Receive ready flags, flow-control, and inter-chip communication in shared IX Bus mode. ...

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... Intel IXP1250 Network Processor Table 26. 64-Bit Bidirectional IX Bus, 3+ MAC Mode (Shared IX Bus Operation Only in This Mode) (Continued) Signal FAST_RX1 FAST_RX2 Shared IX Bus Operation Signals These signals are driven by the IXP1250 IX Bus owner, and are tri-stated when the IXP1250 does not own the ...

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... PORTCTL_L[1:0] FDAT [31:0] FBE_L[3:0] FPS[2:0] RxFAIL SOP EOP [2] PORTCTL_L[3:2] FDAT[63:32] FBE_L[7:4] GPIO[3:1] TXAXIS SOP32 EOP32 [4] [2] [3] [1] [3] ® Intel IXP1250 Network Processor 3.3V MAC0 wireor CINT[7:0] [7: FLCTL[7:0] e FCLK RxRDY[7:0] TxRDY[7:0] RxCTL_L TxCTL_L RxSEL_L RxFDAT_L[31:0] RxFBE_L[3:0] RxFPS[2:0] RxFail RxSOP RxEOP TxSEL_L ...

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... Intel IXP1250 Network Processor Table 27. 32-Bit Unidirectional IX Bus, 1-2 MAC Mode Transmit Path Signals GPIO[3:1] PORTCTL_L[3:2] TXASIS FBE_L[7:4] FDAT[63:31] Receive Path Signals FPS[2:0] PORTCTL_L[1:0] SOP EOP RXFAIL FBE_L[3:0] FDAT[31:0] Control Signals Common to both Transmit/Receive Paths GPIO[0] RDYCTL_L[4 RDYCTL_L[3:0] RDYBUS[7:0] TK_IN ...

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... FBE_L[3:0] FPS[2:0] RxFAIL SOP EOP 2 > 4 decoder GPIO[0] [3:0] [ PORTCTL_L[3:2] D FCLK FDAT[63:32] FBE_L[7:4] GPIO[3:1] TXAXIS SOP32 EOP32 [3] [3] ® Intel IXP1250 Network Processor 3.3V MAC0 wireor CINT[7:0] D [3] Q FLCTL[7:0] e FCLK RxRDY[7:0] TxRDY[7:0] [11] RxCTL_L [7] TxCTL_L RxSEL_L RxFDAT_L[31:0] RxFBE_L[3:0] RxFPS[2:0] RxFail RxSOP RxEOP ...

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... Intel IXP1250 Network Processor Table 28. 32-bit Unidirectional IX Bus, 3+ MAC Mode Transmit Path Signals GPIO[3:1] PORTCTL_L[3:2] GPIO[0] TXAXIS FBE_L[7:4] FDAT[63:31] Receive Path Signals FPS[2:0] PORTCTL_L[1:0] RDYCTL_L[4] SOP EOP RXFAIL FBE_L[3:0] FDAT[31:0] Control Signals Common to both Transmit/Receive Paths RDYCTL_L[3:0] RDYBUS[7:0] TK_IN TK_OUT ...

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... Not used Not used Rx/Tx Data Rx/Tx Data Rx/Tx Byte Enables Rx/Tx Byte Enables Rx/Tx SOP Rx/Tx EOP Not used ® Intel IXP1250 Network Processor 32-bit 32-bit Unidirectional 1-2 Unidirectional 3+ MAC mode MAC mode If RDYCTL_L[ XX00 MAC0 RxSEL XX01 MAC1 RxSEL ...

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... Intel IXP1250 Network Processor Table 29. IX Bus Decode Table Listed by Operating Mode Type (Continued) PIN NAME Bidirectional 1-2 EOP/EOP_TX Not used MAC1 Flw Ctl RDYCTL_L[4] enable when low x1111 NOP x1110 MAC0 Rx RDYCTL_L[4:0] x1101 MAC0 Tx x1011 MAC1 Rx x0111 MAC1 Tx 64 ...

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... PCI AD[31:0] PCI CBE_L[3:0] PCI FRAME_L PCI IRDY_L PCI PAR PCI IDSEL Datasheet Intel Pin Name Pin Reset State output, low output, low output, low output, high output, high output, high output, high output, high output, high output, high output, high ...

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... Intel IXP1250 Network Processor Table 30. Pin State During Reset (Continued) Function PCI PCI_CFN[0] PCI PCI_CFN[1] PCI PCI_IRQ_L PCI PCI_RST_L PCI PERR_L PCI SERR_L PCI STOP_L PCI DEVSEL_L PCI TRDY_L PCI GNT_L[1:0] PCI REQ_L[1:0] IX Bus FCLK IX Bus FDAT[63:0] IX Bus FBE_L[7:4] IX Bus ...

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... Pulldown these signals to VSS: NA/SACLK, FAST_RX1, FAST_RX2. For shared IX Bus operation recommended to pullup PORTCTL_L[3:0] and, additionally, FPS[2:0] and TXAXIS at the designer’s discretion. Typical pullup/pulldown resistor values are in the range of 5-10 KOhms. Datasheet Intel Pin Name Pin Reset State input input ...

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... Intel IXP1250 Network Processor 4.0 Electrical Specifications This chapter specifies the following electrical behavior of the IXP1250: • Absolute maximum ratings. • DC specifications. • AC timing specifications for the following signal interfaces: — PXTAL Clock input. — PCI Bus Interface. — IX Bus Interface. ...

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... Typical Maximum Typical 3.2 W 3.7 W 3.9 W 0.6 W 0.9 W 0.58 W 3.80 W 4.6 W 4.48 W Table ® Intel IXP1250 Network Processor Maximum Comment 3.6 V 3.3 V supply 125°C (VDDX - VDD) or 1.8 V (VDDX - VDDP1) Maximum Comment Tjmax to be managed to stay below 100°C. 70°C (see the Heatsink ...

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... Intel IXP1250 Network Processor Table 34. Maximum and Typical Bus Loading Used for the Power Calculations Maximum Power Load for Core Freq/ IX Bus Freq 166 MHz/66 MHz (Commercial Temperature) SDRAM Bus 8 5 SRAM Bus Bus load is defined as input capacitance equivalent to a CMOS gate + minimal trace length capacitance, typically 8 pF. The customer is responsible for managing the signal integrity and external power issues that occur with increased IXP1200 Bus loading in their application to ensure reliable sys- tem operation ...

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... Input Low Voltage O1: Ioh = -2 mA Output High O3: Ioh = -8 mA Voltage O4: Ioh = -4 mA O5: Ioh = -4 mA O1: Iol = 2 mA O3: Iol = 8 mA Output Low Voltage O4: Iol = 4 mA O5: Iol = 4 mA Input Leakage 0 Vin VDDX 1 Current Pin Capacitance - ® Intel IXP1250 Network Processor Minimum Maximum 2.0 V --- --- 0 --- 0 ...

Page 72

... Intel IXP1250 Network Processor 4.2.2 Type 2 Driver DC Specifications Table 36 refers to pin types: I2, O2. Table 36. I2 and O2 Pin Types Symbol Input leakage currents include high impedance output leakage for all bidirectional buffers with tri-state outputs. Note: In Table 35 and Table Currents from the chip (chip sourcing) are denoted as negative(-) current. Input leakage currents include high-Z output leakage for all bidirectional buffers with tri-state outputs ...

Page 73

... Clock slew rate 1 2,3,4 Core frequency ) of 165.89 MHz when register PLL_CFG[4:0] = 10000b 166.67 MHz when register PLL_CFG[4:0] = 01111b and 199.0656 MHz when register PLL_CFG[4:0] = 10011b and F ® Intel IXP1250 Network Processor Figure 15 for a T low A8553-01 Typical Maximum Unit 3.6864 3 ...

Page 74

... Intel IXP1250 Network Processor 4.3.3 PXTAL Clock Oscillator Specifications Frequency: Stability: Voltage signal level: Rise/fall time: Duty cycle: 4.3.4 PCI 4.3.4.1 PCI Electrical Specification Conformance The IXP1250 PCI pins support the basic set of PCI electrical specifications in the PCI Local Bus Specification, Revision 2 ...

Page 75

... VDDX for 3.3 volt PCI signals test Datasheet Parameter Minimum PCI_CLK cycle time 30 PCI_CLK high time 11 PCI_CLK low time PCI_CLK slew rate 1 F /PCI Clock Ratio 2:1 core T val(max ® Intel IXP1250 Network Processor Maximum Unit ns --- ns --- ns 4 V/ns V test T val(min) T off T h A8555-0 75 ...

Page 76

... Intel IXP1250 Network Processor 4.3.4.3 PCI Bus Signals Timing Table 40. 33 MHz PCI Signal Timing Symbol CLK to signal valid delay, bused 1 T val signals 1 T CLK to signal valid delay, val (point-to-point) point-to-point signals 3 T Float to active delay Active to float delay ...

Page 77

... MHz after a hard reset when PXTAL is 3.6864 MHz. Figure 16. RESET_IN_L Timing Diagram VDD: VDDX, VDDP, VDD_REF RESET_IN# sram_rst_1 [note 1] GPIO<3> TK_OUT Note 1: Internal signal to the IXP1200. Datasheet Intel Parameter Minimum 150 RST ® IXP1250 Network Processor Maximum ...

Page 78

... Intel IXP1250 Network Processor 4.3.6 IEEE 1149.1 The following pins are considered IEEE 1149.1 compliance pins: RESET_IN_L PCI_CLK SCAN_EN TCK_BYP TSTCLK The following pins are not connected to the Boundary Scan ring: RESET_IN_L PCI_CLK SCAN_EN TCK_BYP TSTCLK TCK TMS TDI TDO TRST_L Caution: A clock signal must be applied to the core of the IXP1250 when using IEEE 1149 ...

Page 79

... IEEE 1149.1 Timing Specifications Figure 17. IEEE 1149.1/Boundary-Scan General Timing Datasheet Tbscl tck tms, tdi Tbsis Tbsih tdo Tbsoh Tbsod Data In Tbsss Tbssh Data Out Tbsdh Tbsdd ® Intel IXP1250 Network Processor Tbsch A8557-01 79 ...

Page 80

... Intel IXP1250 Network Processor Figure 18. IEEE 1149.1/Boundary-Scan Tri-State Timing Data Out Table 43 shows the IEEE 1149.1/boundary-scan interface timing specifications. Table 43. IEEE 1149.1/Boundary-Scan Interface Timing Symbol Freq TCK frequency T TCK low period bscl T TCK high period bsch T TDI,TMS setup time bsis ...

Page 81

... Clock frequency 10 1 Cycle time 9.62 Clock high time 3.8 Clock low time 3.8 2 Clock peak to peak 0.6*VDDX 3 Clock rise/fall time 1 F /FCLK Clock Ratio 1.5:1 core ® Intel IXP1250 Network Processor T low A8573-01 Maximum Unit 1 104 MHz 100 ns --- ns --- ns --- ...

Page 82

... Intel IXP1250 Network Processor 4.3.7.2 IX Bus Signals Timing Figure 20. IX Bus Signals Timing CLK Outputs Inputs Table 45. IX Bus Signals Timing Symbol Parameter T Clock to output delay val Data input setup time before T su clock Data input hold time from T h clock ...

Page 83

... Intel IXP1250 Network Processor Minimum Derating (ns/pF) 66 MHz 85 MHz 104 MHz 0.03 0.025 0.015 0.03 0.025 0.015 0.03 0.025 0.015 0.03 0.025 0.015 ...

Page 84

FCLK MAC0/Rx A PORTCTL_L[0] PORTCTL_L[1] PORTCTL_L[2] PORTCTL_L[3] FPS[2:0] Port A FDAT[63:0] Ra4 Ra5 Ra6 Ra7 Tb0 Ra0 Ra1 Ra2 Ra3 SOP EOP FBE_L[7:0] int_1250_OE Notes: int_1250_OE is not an IXP1250 signal shown to indicate when the IXP1250 drives ...

Page 85

FCLK PORTCTL_L[3:0] MAC0/Rx A ext_MAC0_Rx_L ext_MAC1_Tx_L ext_MAC2_Rx_L FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1250_OE is ...

Page 86

FCLK PORTCTL_L[3:0] MAC0/ Select MAC1/Tx B ext_MAC0_Rx_L ext_MAC1_Tx_L ext_MAC2_Rx_L ext_MAC3_Tx_L FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra4 Ra5 Ra6 Ra7 Tb0 Tb1 Tb2 Tb3 Tb6 Tb7 SOP EOP FBE_L[7:0] Int_1250_OE Notes: Signals using prefix "ext_" are outputs of ...

Page 87

... Figure 24. 64-Bit Bidirectional IX Bus Timing - Consecutive Receive and Transmit, EOP on 7th Data Return with Status VDD: VDDX, VDDP, VDD_REF RESET_IN_L sram_rst_1 [note 1] GPIO<3> TK_OUT Note 1: Internal signal to the Intel® IXP1250 processor. Datasheet ® Intel IXP1250 Network Processor t RST 509 PXTAL Cycles ...

Page 88

FCLK PORTCTL_L[3:0] MAC0/Rx A ext_MAC0_Rx_L ext_MAC1_Tx_L ext_MAC2_Rx_L FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 RaS SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1250_OE is not ...

Page 89

FCLK PORTCTL_L[3:0] MAC0/ Select ext_MAC0_Rx_L ext_MAC1_Tx_L ext_MAC2_Rx_L FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 RaS SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1250_OE is ...

Page 90

FCLK No Select PORTCTL_L[3:0] MAC0/Rx A ext_MAC0_Rx_L ext_MAC1_Tx_L ext_MAC2_Rx_L FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 RaS SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1250_OE is not ...

Page 91

FCLK PORTCTL_L[3:0] MAC0/ Select ext_MAC0_Rx_L ext_MAC1_Tx_L ext_MAC2_Rx_L FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 RaS SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1250_OE is not an ...

Page 92

FCLK No Select PORTCTL_L[3:0] MAC0/ Sel ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L FPS[2:0] Port A FDAT[63:0] Ra0 SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1250_OE is not an IXP1250 ...

Page 93

FCLK No Select No Select PORTCTL_L[3:0] MAC0/Rx A ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ ...

Page 94

FCLK No PORTCTL_L[3:0] MAC0/Rx A Sel ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L Port A FPS[2:0] FDAT[63:0] Ra4 Ra5 Ra6 Ra7 Ra0 Ra1 Ra2 Ra3 SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. ...

Page 95

FCLK No Select PORTCTL_L[3:0] MAC0/Rx A ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 RaS SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. ...

Page 96

FCLK No Select PORTCTL_L[3:0] MAC0/Rx A ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L FPS[2:0] Port A FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 RaS SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1250_OE ...

Page 97

FCLK No PORTCTL_L[3:0] MAC0/Rx A Sel ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L FPS[2:0] Port FDAT[63:0] Ra0 Ra1 Ra2 Ra3 SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ ...

Page 98

FCLK No Sel No Sel PORTCTL_L[7 :0] MAC0/Rx A ext_MAC0_Rx_L ext_MAC1_Rx_L Port A Fetch-9 FPS[2:0] FDAT[63:0] Ra0 Ra1 Ra2 Ra3 Ra4 Ra5 Ra6 Ra7 Ra8 SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder ...

Page 99

FCLK No Sel No Sel PORTCTL_L[3:0] MAC0/Tx A ext_MAC0_Tx_L ext_MAC1_Tx_L ext_MAC2_Tx_L FPS[2:0] Port A FDAT[63:0] Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ ...

Page 100

FCLK No Sel No Sel PORTCTL_L[3:0] MAC0/Tx A ext_MAC0_Tx_L ext_MAC1_Tx_L ext_MAC2_Tx_L FPS[2:0] Port A FDAT[63:0] TaP Ta0 Ta1 Ta2 Ta3 Ta7 Ta4 Ta5 Ta6 SOP EOP FBE_L[7:0] int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in ...

Page 101

FCLK No Sel PORTCTL_L[1 :0] MAC0/Rx A MAC1/ used with PORTCTL_L RDYCTL_L[4] 3+ MAC mode only ) ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L ext_MAC3_Rx_L Port A FPS[2: FDAT[31:0] Ra0 Ra1 Ra2 Ra3 Rb0 Rb1 Rb2 Rb3 13 14 ...

Page 102

FCLK No Sel No Sel PORTCTL_L[1:0] MAC0/Rx A MAC1/ used with PORTCTL_L 3+ MAC mode only ) RDYCTL_L[4] ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L ext_MAC3_Rx_L FPS[2:0] Port A Port B Ra FDAT[31: Ra0 Ra1 Rb0 Rb1 ...

Page 103

FCLK No Sel No Sel PORTCTL_L[1:0] MAC0/Rx A MAC1/ used with PORTCTL_L RDYCTL_L[4] 3+ MAC mode only ) ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L ext_MAC3_Rx_L Port A FPS[2: FDAT[31:0] Ra0 Ra1 Ra2 Ra3 RaS Rb0 Rb1 Rb2 Rb3 13 ...

Page 104

FCLK No Sel No Sel PORTCTL_L[1:0] MAC0/Rx A MAC1/ used with PORTCTL_L 3+ MAC mode only ) RDYCTL_L[4] ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L ext_MAC3_Rx_L FPS[2:0] Port A Ra FDAT[31:0] Ra0 Ra1 Ra2 Ra3 RaS Rb0 Rb1 Rb2 Rb3 13 SOP ...

Page 105

FCLK No Sel No Sel PORTCTL_L[1:0] MAC0/Rx A MAC1/ used with PORTCTL_L 3+ MAC mode only ) RDYCTL_L[4] ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L ext_MAC3_Rx_L Port A FPS[2:0] Ra FDAT[31:0] Ra0 Ra1 Ra2 RaS Rb0 Rb1 Rb2 12 SOP EOP FBE_L[3:0] ...

Page 106

FCLK No PORTCTL_L[1:0] MAC0/Rx A MAC0/Rx B Sel ( used with PORTCTL_L 3+ MAC mode only ) RDYCTL_L[4] ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L ext_MAC3_Rx_L FPS[2:0] Port FDAT[31:0] Ra1 Rb0 Rb1 Ra0 SOP EOP FBE_L[3:0] Notes: ...

Page 107

FCLK No No PORTCTL_L[1:0] MAC0/Rx A MAC1/Rx B Sel Sel ( used with PORTCTL_L 3+ MAC mode only ) RDYCTL_L[4] ext_MAC0_Rx_L ext_MAC1_Rx_L ext_MAC2_Rx_L ext_MAC3_Rx_L Port A Port B FPS[2:0] FDAT[31: Ra0 Ra1 Rb0 Rb1 ...

Page 108

FCLK No Sel No Sel PORTCTL_L[3:2] MAC0/Tx A GPIO[0] ( used with PORTCTL_L 3+ MAC mode only ) ext_MAC0_Tx_L ext_MAC1_Tx_L ext_MAC2_Tx_L Port A GPIO[3:1] FDAT[31:0] Ta0 Ta1 Ta2 Ta3 Ta15 SOP32 EOP32 FBE_L[7:4] Notes: Signals using prefix "ext_" are outputs ...

Page 109

FCLK No Sel PORTCTL_L[3:2] MAC0/Tx A GPIO[0] ( used with PORTCTL_L 3+ MAC mode only ) ext_MAC0_Tx_L ext_MAC1_Tx_L ext_MAC2_Tx_L Port A GPIO[3:1] FDAT[31:0] TaP TaP Ta0 Ta1 Ta2 Ta14 Ta15 0 1 SOP32 EOP32 FBE_L[7:4] Notes: Signals using prefix "ext_" ...

Page 110

FCLK No PORTCTL_L[3:0] FastPort/Rx Port 0 req_L1 Sel ext_MAC0_Rx_L FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP EOP FBE_L[7:0] register FP_READY_WAIT=0 FAST_RX1 int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in ...

Page 111

FCLK No PORTCTL_L[3:0] FastPort/Rx Port 0 req_L1 Sel ext_MAC0_Rx_L FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP EOP FBE_L[7:0] register FP_READY_WAIT=5 FAST_RX1 int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in ...

Page 112

FCLK No PORTCTL_L[3:0] FastPort/Rx Port 0 req_L1 No Select - 5 clks Sel ext_MAC0_Rx_L FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP EOP FBE_L[7:0] register FP_READY_WAIT=0 FAST_RX1 int_1250_OE Notes: Signals using prefix "ext_" are outputs ...

Page 113

FCLK PORTCTL_L[3:0] FastPort/Rx Port 0 req_L1 No Select-5 clks ext_MAC0_Rx_L FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP EOP FBE_L[7:0] register FP_READY_WAIT=5 FAST_RX1 int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder ...

Page 114

FastPort request #2 pending FCLK PORTCTL_L[3:0] FastPort/Rx Port 0 req_L1 No Sel ext_MAC0_Rx_L FPS[2:0] FDAT[63:0] Rf0 Rf1 SOP/ EOP FBE_L[7:0] register FP_READY_WAIT=0 FAST_RX1 int_1250_OE Notes: Signals using prefix "ext_" are outputs of an external decoder in 3+ MAC mode. int_1250_OE ...

Page 115

FCLK No PORTCTL_L[3:0] FastPort/Rx Port 0 req_L1 Sel ext_MAC0_Rx_L FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP EOP FBE_L[7:0] register FP_READY_WAIT = don't care FAST_RX1 int_1250_OE Notes: Signals using prefix "ext_" are outputs of an ...

Page 116

FCLK No Sel PORTCTL_L[3:0] FastPort/Rx Port 0 req_L1 FastPort/Rx Port 1 req_L1 ext_MAC0_Rx_L FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP EOP FBE_L[7:0] register FP_READY_WAIT=0 FAST_RX1 FAST_RX for Port 1 req_L1 sampled FAST_RX2 int_1250_OE Notes: ...

Page 117

FCLK PORTCTL_L[3:0] FastPort/Rx Port 0 req_L1 ext_MAC0_Rx_L FPS[2:0] Port 0 FDAT[63:0] Rf0 Rf1 Rf2 Rf3 Rf4 Rf5 Rf6 Rf7 SOP EOP FBE_L[7:0] register FP_READY_WAIT=0 FAST_RX1 FAST_RX for Port 1 req_L1 sampled- pending request cancelled FAST_RX2 int_1250_OE Notes: Signals using prefix ...

Page 118

... Intel IXP1250 Network Processor 4.3.7.4 RDYBus Figure 55. Consecutive Fetch Ready Flags, 1-2 MAC Mode (with No External Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=1 FCLK RDYCTL_L[0] RDYCTL_L[1] RDYCTL_L[2] RDYCTL_L[3] RDYBUS[7:0] Figure 56. Consecutive Fetch Ready Flags, 3+ MAC Mode (with External Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 FCLK RDYCTL_L[4:0] NOP ext_MAC0_RxSel_L ...

Page 119

... GPIO[0] RDYCTL_L[4] ext_MAC0_FC_ data ext_MAC1_FC_ data Notes: Configuration used an external Flow Control latch, and no external decoder. Signals using prefix "ext_" are outputs of the external latch. Datasheet Intel Get1, One Longword NOP NOP MAC TxRdy Flags Byte 3 Byte 2 Byte 1 Byte 0 MAC0/ TxRdy ...

Page 120

... Intel IXP1250 Network Processor Figure 59. Ready Bus Control Timing, Fetch Ready Flags - Flow Control - Fetch Ready Flags, 3+ MAC Mode (with External Registered Decoder) - RDYBUS_TEMPLATE_CTL[10]=0 FCLK RDYCTL_L[4:0] ext_MAC0_RxRdy_L ext_MAC1_RxRdy_L ext_MAC2_RxRdy_L ext_MAC0_FC_L RDYBUS[7:0] Notes: Configuration uses an external Flow Control latch, and an external registered decoder. ...

Page 121

... TK_OUT _L1 (is TK_IN to _L2 ) TK_OUT _L2 FDAT[63:0] PORTCTL_L[7:0] Notes Driven by the Intel if the transfer Driven high for one cycle by the IXP1200 Network Processor _L2 (no port is selected), then tristated Weak external pull-up resistors are recommended on PORTCTL_L[7:0], FPS[2:0] and TXAXIS. 4.3.8 SRAM Interface 4 ...

Page 122

... Intel IXP1250 Network Processor Table 47. SRAM SCLK Signal AC Parameter Measurements Symbol Freq Clock frequency T Cycle time cyc T Clock high time high T Clock low time low SCLK rise/fall time r f 4.3.8.2 SRAM Bus Signal Timing Figure 62. SRAM Bus Signal Timing SCLK ...

Page 123

... Intel IXP1250 Network Processor Maximum (IXP1250 Core Speed) Unit 232 166 200 232 MHz MHz MHz MHz 0.5 5.0 4.5 3.35 ns 0.5 5 ...

Page 124

... Intel IXP1250 Network Processor 4.3.8.3 SRAM Bus - SRAM Signal Protocol and Timing Figure 63. Pipelined SRAM Read Burst of Eight Longwords SCLK SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] A[18:0] SWE_L SOE_L DQ[31:0] 124 CE_L<3:0> = 1110 D(A0) D(A1) D(A2) D(A3) D(A4) D(A5) D(A6) ...

Page 125

... Figure 64. Pipelined SRAM Write Burst of Eight Longwords SCLK SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] A[18:0] SWE_L SOE_L DQ[31:0] Datasheet ® Intel IXP1250 Network Processor CE_L<3:0> = 1110 D(A0) D(A1) D(A2) D(A3) D(A4) D(A5) D(A6) D(A7) A8611-01 125 ...

Page 126

... Intel IXP1250 Network Processor Figure 65. Pipelined SRAM Read Burst of Four From Bank 0 Followed by Write Burst of Four From Bank 8 SCLK SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] A[18:0] SWE_L SOE_L DQ[31:0] Note 1: There is always a 1 clock cycle idle state on the data bus when switching from read to write. ...

Page 127

... SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] A[18:0] SWE_L SOE_L DQ[31:0] Note 1: There is always a one clock cycle idle state on the data bus when switched from a read to write cycle. Datasheet ® Intel CE_L<3:0> = 1110 D(A1) D(A2) D(A3) D(A0) Idle State [note 1] IXP1250 Network Processor CE_L< ...

Page 128

... Intel IXP1250 Network Processor Figure 67. Flowthrough SRAM Read Burst of Eight Longwords SACLK SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] A[18:0] SWE_L SOE_L DQ[31:0] 128 CE_L<3:0> = 1110 D(A0) D(A1) D(A2) D(A3) D(A4) D(A5) D(A6) A7 D(A7) A8614-01 Datasheet ...

Page 129

... SRAM SlowPort Cycle Count (Does not apply to BootROM) BootROM Cycle Count (11) Cycle time = Cycle Count + 1 (12 cycles) 15:8 7 SLOW__EN_L Deassert. (3) SLOW__EN_L Assert (10) SLOW_RD_L/SLOW_WE_L Deassert. (5) ® Intel IXP1250 Network Processor Valid Address Valid Valid SLOW_EN_L Deassert. (3) SLOW_RD_L Deassert. (5) ...

Page 130

... Intel IXP1250 Network Processor Figure 69. BootROM Write A[18:0] DQ[31:0] SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] Externally Generated Signal BootROM Chip select signal SLOW_EN_L or CE_L<3:0> Cycle Count = Example for the following setting in SRAM registers SRAM_SLOW_CONFIG 31:16 RES SRAM_BOOT_CONFIG 31:24 23: SLOW_RD_L/SLOW_WE_L Assert. (9) ...

Page 131

... Figure 70. Pipelined SRAM Two Longword Burst Read Followed by BootROM Write SCLK A[18:0] DQ[31:0] Buffered DQ[31:0] SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] SWE_L SOE_L BootROM_CE_L[3:0] Datasheet Intel A2 A1 D(A1) D(A1) D(A2) CE_L<3:0> = 1110 BootROM_CE_L = -(-SLOW_EN_L & -CE_L) ® IXP1250 Network Processor A3 A3 D(A3) D(A3) D(A3) ...

Page 132

... Intel IXP1250 Network Processor 4.3.8.6 SRAM Bus - Slow-Port Device Signal Protocol and Timing Figure 71. SRAM SlowPort Read DQ[31:0] SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L MCE_L Externally Generated Signal SRAM SlowPort Chip select signal - MCE_L & address Cycle Count = Example for the following setting in SRAM registers ...

Page 133

... SRAM SlowPort Cycle Count (11) Cycle time = Cycle Count + 1 (12 cycles) BootROM Cycle Count (Does not apply to SRAM SlowPort) 15:8 7 SLOW__EN_L Deassert. (3) SLOW_RD_L/SLOW_WE_L Deassert. (5) SLOW__EN_L Assert (10) ® Intel IXP1250 Network Processor Valid Address Valid Data SLOW_EN_L Deassert. (3) SLOW_RD_L Deassert. (5) ...

Page 134

... Intel IXP1250 Network Processor Figure 73. SRAM SlowPort RDY_L SCLK A[18:0] DQ[31:0] SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L MCE_L ext_CE_L (MCE_L.AND.Ax) Cycle_count Register Settings used for these timings: SRAM_SLOW_CONFIG=000A:0B0Fh where RDY_L Pause State=Ah, BCC=0Bh, and SCC=0Fh SRAM_SLOWPORT_CONFIG=0D0E:0501h where SRWA=0Dh, SCEA=0Eh, SRWD=05h, SCED=01 SRAM_CSR=0009:4810h where < ...

Page 135

... Figure 74. Pipelined SRAM Two Longword Burst Read Followed By SlowPort Write SCLK A[18:0] DQ[31:0] Buffered DQ[31:0] MCE_L SLOW_EN_L MRD_L FWE_L HIGH_EN_L LOW_EN_L CE_L[3:0] SWE_L SOE_L BootROM_CE_L[3:0] Datasheet ® Intel IXP1250 Network Processor D(A1) D(A2) D(A3) CE_L<3:0> = 1110 A3 D(A3) D(A3) D(A3) A8621-01 135 ...

Page 136

... Intel IXP1250 Network Processor 4.3.9 SDRAM Interface 4.3.9.1 SDCLK AC Parameter Measurements Figure 75. SDCLK AC Timing Diagram Vt1 = 0.5*VDDX Vt2 = 0.4*VDDX Vt3 = 0.3*VDDX Table 50. SDCLK AC Parameter Measurements Symbol Freq Clock frequency T Cycle time cyc T Clock high time high T Clock low time low ...

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... Table 52. (min) parameters are tested under 0 pF load best case conditions (Vdd=2.1, ctl , the T timings are both what the tester must measure and what the sup su ® Intel IXP1250 Network Processor T val(min) T off ctl(min) A8623-01 Maximum (IXP1250 Core Speed) ...

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... Intel IXP1250 Network Processor Table 52. Signal Delay Deratings for T Signal SDCLK DQM WE_L RAS_L CAS_L MADR[14:0] MDATA[63:0] MDATA_ECC[7:0] 4.3.9.3 SDRAM Signal Protocol This section describes the SDRAM timing parameters referenced in the SDRAM timing diagrams that follow. This nomenclature is consistent with most JEDEC standard SDRAM devices. ...

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... Most PC100 type SDRAM devices allow a zero-delay read-write turnaround. However, tHZmax for PC100 devices is 5.4ns (CASL= (CASL=3) and tON for the IXP1250 clock tRWT would be required to avoid bus contention. Datasheet ® Intel IXP1250 Network Processor 139 ...

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... Intel IXP1250 Network Processor Figure 77. SDRAM Initialization Sequence SDCLK RAS_L CAS_L WE_L MADR MDAT DQM Notes: 1. Number of total initialization phase refresh cycles programmed as INIT_RFRSH value in register SDRAM_MEMINIT. 2. Burst length and CAS latency values programmed as BURSTL value in register SDRAM_MEMCTL0 emitted in this cycle. ...

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... SDCLK RAS_L CAS_L WE_L MADR MDAT DQM Notes: 1. Parameters tRWT, tDPL, tDQZ, tRC, tRRD, tRCD, tRASmin, and tRP programmed into register SDRAM_MEMCTL1 2. CAS Latency value (CASL programmed in SDRAM_MEMCTL0 Datasheet Intel tRASmin tRCD Precharge Read command Activate command command (terminates access) ® ...

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... Intel IXP1250 Network Processor Figure 79. SDRAM Write Cycle SDCLK RAS_L CAS_L WE_L MADR MDAT DQM Notes: 1. Parameters tRWT, tDPL, tDQZ, tRC, tRRD, tRCD, tRASmin, and tRP programmed into register SDRAM_MEMCTL1 2. CAS Latency value (CASL programmed in SDRAM_MEMCTL0 142 tRASmin tRCD tDPL ...

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... Are asynchronous relative to any device outside the IXP1250. Datasheet tRASmin tRCD tDQZ DQM remains high Activate Read during modify command command ® Intel IXP1250 Network Processor tDPL tRWT Write DQM remains high command until next read or write command Precharge command A8627-01 ...

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... IXP1250 Network Processor 5.0 Mechanical Specifications 5.1 Package Dimensions The IXP1250 is contained in a 520-HL-PBGA package, as shown in Figure 81. IXP1250 Part Marking Pin 1 144 i GCIXP1250xx FFFFFFFF INTEL M C 2001 xxxxxxxSz YWW PHILLIPPINES Figure 81. Name FPO # Intel Legal BSMC (ALT# & DATE CODE, COO) A8566-02 ...

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... Figure 82. 520-HL-PBGA Package - Bottom View Figure 83. IXP1250 Side View Datasheet ® Intel IXP1250 Network Processor Ball 1 6 Corner A8628-01 bbb C Seating Plane C ddd 3 A8629-01 145 ...

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... Intel IXP1250 Network Processor Figure 84. IXP1250 A-A Section View T 146 0.20 MIN ccc A8630-01 Datasheet ...

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... When there is an odd number of solder balls in the outer row, S=0.000; when there is an even number of solder balls in the outer row, the value S=e/2. S can be either 0.000 or e/2 for each variation. 9. Equivalent to ANAM P/N 71290 Datasheet Intel Definition Minimum — 0.50 0.80 — ...

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