GCIXP1250BC 837414 Intel, GCIXP1250BC 837414 Datasheet - Page 36

• Manufacturer Part Number: GCIXP1250BC 837414
• Manufacturer: Intel

Specifications of GCIXP1250BC 837414

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
36
Table 15. IX Bus Interface Pins (Continued)
®
IXP1250 Network Processor
EOP
EOP32
SOP32
TK_OUT
TK_IN
Totals:
IX Bus Signal
Names
AJ12
AL7
AH8
AA29
AA28
Number
Pin
O4
O4
O1
I1
I1/TS
Type
1
1
1
1
1
103
Total
End of Packet Indication.
Transmit End Of Packet
32-bit unidirectional IX Bus modes EOP32 is Transmit End
of Packet output according to values programmed in the
TFIFO control field.
Transmit Start Of Packet Indication
Token Output.
Used to pass ownership of the IX Bus in a shared IX Bus
system in 64-bit bidirectional IX Bus mode.
In 32-bit unidirectional mode this bit is unused and should be
left unconnected.
Token Input.
64-bit bidirectional IX Bus Mode: A high-to-low transition
indicates that this device has been given ownership of the IX
Bus in a shared IX Bus system.
In 32-bit unidirectional mode, this input is not used and
should be pulled high.
During Reset, used to configure the device as initial IX Bus
owner. 1= device is initial owner, 0= device does not own the
IX Bus. TK_IN is sampled from the rising edge of
RESET_IN_L.
• Receive End of Packet Input in 32-bit unidirectional IX
• Input/Output in 64-bit bidirectional IX Bus mode. EOP is
• In a shared IX Bus system, this pin will be tri-stated
• Output in 32-bit unidirectional IX Bus modes. SOP32 is
Bus mode.
Transmit End of Packet output according to values
programmed in the TFIFO control field. Is Receive End
of Packet input during receive cycles.
when passing ownership of the IX Bus.
Transmit Start of Packet output during transmit
according to values programmed in the TFIFO control
field.
Pin Descriptions
Datasheet