GCIXP1250BC 837414 Intel, GCIXP1250BC 837414 Datasheet - Page 30

• Manufacturer Part Number: GCIXP1250BC 837414
• Manufacturer: Intel

Specifications of GCIXP1250BC 837414

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
30
Table 13. SRAM Interface Pins (Continued)
®
IXP1250 Network Processor
CE_L[3:0]
SCLK
SOE_L
SWE_L
LOW_EN_L
HIGH_EN_L
SLOW_EN_L
NA/SACLK
FWE_L
MRD_L
MCE_L
Totals:
SRAM Interface
Signal Names
[3]
[2]
[1]
[0]
D24
A25
E24
B25
W30
W29
Y31
D25
B26
Y29
B23
Y30
W27
W28
Number
Pin
O4
O3
O4
O4
O4
I1/O4
O4
I1
O4
O4
O4
Type
4
1
1
1
1
1
1
1
1
1
1
65
Total
SRAM Bus chip enable outputs. Internally decoded from
SRAM address. Valid during SRAM and BootROM
accesses.
SRAM clock output - Frequency is one half the speed of
the Core clock (½ * F
SRAM output enable.
SRAM write enable.
Low order SRAM bank enable and buffer direction select
for slow interface.
High-order SRAM bank enable output and Flash
PROM/BootROM read enable or asynchronous Ready
input from I/O devices. The pin function is determined by
programming SRAM_CSR[19] =1, which enables RDY_L
or SRAM_CSR[19] =0, which enables the HIGH_EN_L
function.
Slow device enable: 0 = Slow device (BootROM or
SlowPort), 1=SRAM.
SRAM clock input, used to compensate for skew in data
path when using Flowthru SRAMs. Must be connected to
SCLK output when using Flowthru devices. Not used with
Pipelined devices and should be pulled low.
Asynchronous interface write enable (BootROM or MAC
devices).
Slow asynchronous interface read enable output.
Slow asynchronous interface chip enable output.
Pin Descriptions
core
).
Datasheet