GCIXP1250BC 837414 Intel, GCIXP1250BC 837414 Datasheet - Page 40

• Manufacturer Part Number: GCIXP1250BC 837414
• Manufacturer: Intel

Specifications of GCIXP1250BC 837414

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
40
Table 18. PCI Interface Pins (Continued)
®
IXP1250 Network Processor
PCI_CFN
GNT_L[0]
REQ_L[0]
GNT_L[1]
REQ_L[1]
Totals:
Signal Names
PCI Interface
[1]
[0]
A23
E22
C20
A20
B20
E19
Number
Pin
I2
I2/O2
I2/O2
I2/O2
I2/O2
Type
2
1
1
1
1
54
Total
PCI Central Function and arbitration select inputs. Sampled
on the rising edge of RESET_IN_L.
When = 11, the IXP1250 provides the PCI Central Function
and arbitration support and:
When = 00, PCI Central Function and arbitration is disabled
and:
Values of 10 and 01 are reserved for future use.
PCI Bus Master Grant 1.
Internal PCI arbiter is enabled (PCI_CFN[1:0] = 11): Pin is an
output to grant a PCI device 1 control of the PCI Bus. (The
IXP1250 is PCI device 0 in this case)
Internal PCI arbiter is disabled (PCI_CFN[1:0] = 00): Pin is
an input that indicates that the IXP1250 can assert
FRAME_L and become the bus master. If the IXP1250 is idle
when GNT_L[0] is asserted, it parks the PCI Bus.
PCI Bus Master Request 1.
Internal PCI arbiter is enabled (PCI_CFN[1:0] = 11): Pin is an
input indicating an external PCI device is requesting use of
the PCI Bus.
Internal PCI arbiter is disabled (PCI_CFN[1:0] = 00): Pin is
an output indicating that the IXP1250 is requesting use of the
PCI Bus.
PCI Bus Master Grant 2.
Internal PCI arbiter is enabled (PCI_CFN[1:0] = 11): Pin is an
output to grant a PCI device 2 control of the PCI Bus (The
IXP1250 is PCI device 0 in this case).
When Internal PCI arbiter is disabled (PCI_CFN[1:0]=00,
GNT_L[1] should be connected to VDDX through a pullup
resistor of 10 KOhms.
PCI Bus Master Request 2.
Internal PCI arbiter is enabled (PCI_CFN[1:0] = 11): This
input indicates that PCI device 2 is requesting to take control
of the PCI Bus.
Is driven to an output high level when internal PCI arbiter is
disabled (PCI_CFN[1:0] = 00).
• PCI_RST_L is an output asserted by the PCI Unit when
• IXP1250 provides bus parking during reset.
• SERR_L is an input that can generate an interrupt to the
• PCI_RST_L is an input asserted by the Host processor.
• The IXP1250 does not provide bus parking during reset.
initiated by the StrongARM* core.
StrongARM* core.
Pin Descriptions
Datasheet