GCIXP1250BC 837414 Intel, GCIXP1250BC 837414 Datasheet - Page 34

• Manufacturer Part Number: GCIXP1250BC 837414
• Manufacturer: Intel

Specifications of GCIXP1250BC 837414

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Intel
34
Table 15. IX Bus Interface Pins (Continued)
®
IXP1250 Network Processor
FBE_L[7:0]
TXASIS
RXFAIL
FAST_RX1
FAST_RX2
IX Bus Signal
Names
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[10]
[11]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
AK22
AH21
AJ21
AK21
AG20
AH20
AJ20
AK20
AL20
AG19
AH19
AJ19
AK19
AL19
AG18
AH18
AJ18
AK18
AL18
AG17
AH17
AJ17
AK17
AL15
AK15
AJ15
AH15
AG15
AL14
AK14
AJ14
AH14
AG14
AL13
AK13
AJ13
AH13
AG13
AL12
AH12
AG12
AK11
AJ11
Number
Pin
I2/O5/
TS
O4/TS 1
I1/O1/
TS
I1
I1
Type
8
1
1
1
Total
Bidirectional Byte Enables.
64-bit bidirectional IX Bus mode. Bits [7:0] indicate transmit
and receive valid bytes on FDAT[63:0].
32-bit unidirectional IX Bus mode. Bits [7:4] are used to
indicate valid transmit bytes on FDAT[63:32] and bits [3:0]
are used to indicate valid receive bytes on FDAT[31:0].
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
Transmit As Is.
TXASIS states are output according to values programmed
in the TFIFO control field. TXASIS value driven coincident
with SOP/SOP_TX signal.
In a shared IX Bus system, this pin will be tri-stated when
passing ownership of the IX Bus.
Receive Packet Failure. As input, asserted by a MAC device
if a packet was received with errors. Mimics the behavior of
EOP to terminate an IX Bus cycle.
As output, driven when no receive cycle in-progress.
In a shared IX Bus system, these pins will be tri-stated when
passing ownership of the IX Bus.
Ready Input from Fast Port 0 (i.e., Gigabit port). Pulldown
through 10 KOhms to VSS if not used.
Ready Input from Fast Port 1 (i.e., Gigabit port). Pulldown
through 10 KOhms to VSS if not used.
Pin Descriptions
Datasheet