GCIXP1250BC 837414 Intel, GCIXP1250BC 837414 Datasheet - Page 35

• Manufacturer Part Number: GCIXP1250BC 837414
• Manufacturer: Intel

Specifications of GCIXP1250BC 837414

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Datasheet
Table 15. IX Bus Interface Pins (Continued)
RDYCTL_L[4]
RDYCTL_L[3:0]
RDYBUS[7:0]
SOP
IX Bus Signal
Names
[3]
[2]
[1]
[0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
AJ8
AK8
AG9
AL8
AH9
AH11
AK10
AJ10
AH10
AL9
AG10
AK9
AJ9
AK12
Number
Pin
I1
I1/O4/
TS
I1/O4
I1/TS
Type
1
4
8
1
Total
In 64-bit Bidirectional IX Bus Mode:
In 32-bit Unidirectional Mode:
Bidirectional Ready Control signals.
In 64-bit Bidirectional IX Bus Mode:
In 32-bit Unidirectional Mode:
8-Bit Bidirectional Ready Bus data.
Start of Packet indication.
• 1-2 MAC mode: Used as an active low flow control
• 3+ MAC mode: Used in conjunction with
• In a shared IX Bus system the IXP1250 Ready Bus
• 1-2 MAC mode: Used as an active low flow control
• 3+ MAC mode: Used as an active low enable for an
• 1-2 MAC mode: Bits [3:0] are used to enable the
• 3+ MAC mode: The transmit and receive FIFO Ready,
• In a shared IX Bus system the IXP1250 Ready Bus
• 1-2 MAC mode: Bits [3:0] are used to enable the
• 3+ MAC mode: The transmit and receive FIFO ready
• Inputs the Transmit and Receive Ready Flags from IX
• Outputs flow control data to IX Bus devices.
• Data bus for interprocessor communications.
• Receive Start of Packet Input in 32-bit unidirectional IX
• Input/Output in 64-bit bidirectional IX Bus mode. SOP is
• In a shared IX Bus system, this pin will be tri-stated
enable for MAC 1 (GPIO[0] is used as a flow control
enable for MAC 0).
RDYCTL_L[3:0].
Master drives this pin. IXP1250 Ready Bus slave
devices snoop this pin.
enable for MAC 1. GPIO[0] is used as a flow control
enable for MAC 0.
external decoder for the PORTCTL[1:0] signals.
transmit or receive FIFO Ready Flags.
the flow control, and inter-processor communication
enables are decoded from RDYCTL_L[4:0].
Master drives this bus. IXP1250 Ready Bus slave
devices snoop these pins as inputs.
transmit or receive FIFO Ready Flags.
and flow control enables are decoded from
RDYCTL_L[3:0].
Bus devices.
Bus mode.
Transmit Start of Packet output according to values
programmed in the TFIFO control field. Is Receive Start
of Packet input during receive cycles.
when passing ownership of the IX Bus.
Intel
Pin Descriptions
®
IXP1250 Network Processor
35