GCIXP1250BC 837414 Intel, GCIXP1250BC 837414 Datasheet - Page 25

• Manufacturer Part Number: GCIXP1250BC 837414
• Manufacturer: Intel

Specifications of GCIXP1250BC 837414

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2.7.1
2.7.2
2.7.3
2.7.4
Datasheet
Hardware Initiated Reset
The IXP1250 provides the RESET_IN_L pin so that an external device can reset the IXP1250.
Asserting this pin resets the internal functions and generates an external reset via the
RESET_OUT_L pin.
Upon power-up, RESET_IN_L must remain asserted for 150 ms after VDD and VDDX are stable
to properly reset the IXP1250 and ensure that the PXTAL clock input and PLL Clock generator are
stable.
While RESET_IN_L is asserted, the processor is held reset. When RESET_IN_L is released, the
StrongARM* processor begins execution from SRAM address 0 after 512 PXTAL cycles. If
RESET_IN_L is asserted while the StrongARM* core is executing, the current instruction
terminated abnormally and the on-chip caches, MMU, and write buffer are disabled.
The RESET_OUT_L signal remains asserted until deasserted by the StrongARM* core. The
StrongARM* core deasserts the signal by writing bit 15 of the IXP1250_RESET register.
Software Initiated Reset
The StrongARM* core or an external PCI Bus master can reset specific functions in the IXP1250
by writing to the IXP1250_RESET register. In most cases, only the individual Microengines are
reset and the external RESET_OUT_L pin will be asserted via this register. The ability to reset the
other functions is provided for debugging. The SRAM Unit is always reset when the StrongARM*
Core is reset. To ensure a proper reset, the StrongARM* core and the SRAM Unit are held in reset
for 140 system clock cycles after RESET_IN_L is deasserted. The other functions that can be reset
via the IXP1250_RESET register are properly reset when consecutive writes are performed to
assert and deassert the reset.
PCI Initiated Reset
The IXP1250 can be reset by an external PCI Bus master when the IXP1250 is not the PCI Central
Function and arbiter device (PCI_CFG[1:0] = 00) and PCI_RST_L is an input. The entire IXP1250
is reset during a PCI Initiated Reset. When the IXP1250 is assigned as the PCI Central Function
and arbiter device (PCI_CFG[1:0] = 11), the IXP1250 drives PCI_RST_L as an output to the other
devices on the PCI Bus.
Watchdog Timer Initiated Reset
The IXP1250 provides a watchdog timer that can reset the StrongARM* core. The StrongARM*
core should be programmed to reset the watchdog timer periodically to ensure that the timer does
not expire. If the watchdog timer expires, it is assumed the StrongARM* core has ceased executing
instructions properly. The reset generated by the Watchdog Timer will reset each of the functions in
the IXP1250.
Intel
®
IXP1250 Network Processor
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