QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 9

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Non-Core Errata (Sheet 2 of 2)
Core Errata
Specification Changes
Specification Update
No.
No.
31
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36
No.
1
2
3
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1
2
3
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A-0
A-0
Steppings
X
X
X
X
X
X
Stepping
X
X
X
X
X
X
X
X
A-0
Steppings
X
X
X
X
X
X
A-1
A-1
X
X
X
X
X
X
X
X
X
X
X
X
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A-1
X
X
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Page
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Status
No Fix
No Fix
No Fix
No Fix
No Fix
Status
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
Fixed
Status
Fixed
Doc
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Doc
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Doc
Tc1(min) of the PCI-X clock observed to be marginally less than the requirement
specified for the PCI-X (Mode 1, class1) clock jitter.
I2C Control Register reset bit does not function
MSI Hot-Plug Interrupt issue
Under certain conditions, inbound prefetched PCI read requests may return wrong
data to the requestor
Internal Clock Misalignment Can Cause Processor Hang.
Spurious DMA0 End-Of-Transfer Interrupt
Abort is missed when lock command is outstanding
Aborted store that hits the data cache can mark write-back data as dirty
Performance Monitor Unit event 0x1 can be incremented erroneously by unrelated
events
In Special Debug State, back-to-back memory operations—in which the first
instruction aborts—can cause a hang
Accesses to the CP15 ID Register with opcode2 > 001b returns unpredictable
values
Disabling and re-enabling the MMU can hang the core or cause it to execute the
wrong code
Updating the JTAG parallel registers requires an extra TCK rising edge
Non-branch instruction in vector table might execute twice after a thumb mode
exception
Recommended DLL register values
DDR-II JEDEC initialization sequence includes writes to EMRS2 and EMRS3
REFCLK relationship to voltage rails
Case temperature (Tcase) change
PWRGD and RSTIN# sequencing
Internal Clock Misalignment.
Specification Changes
Errata
Errata
Summary Table of Changes
Intel® 80333 I/O Processor
9