QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 34

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Specification Clarifications
7.
Issue:
Status:
8.
Issue:
Status:
9.
Issue:
34
Note: Since a PCIX reset independent of a PCIE reset will result in a reset of the Intel XScale
Back-to-back MCU MMR reads
The memory controller unit (MCU) returns the wrong memory-mapped register (MMR) read data,
when two MMR read transactions are enqueued into the transaction queues at the same time. This
cannot happen from the BIU port as mapping the MMRs to this space is not allowed.
The only way this can occur is for two internal bus devices to request info from the MCU MMRs at
the same time (with different addresses). For example, the BIU (via the Intel XScale
and the ATU (via the host), which is a very unlikely usage model.
No
Reserved IDSELs on A-segment
The Intel® 80333 I/O Processor Developer’s Manual added Table 9, which shows AD24–AD27 as
“reserved” IDSELs for the A-segment. These are reserved so that the Intel XScale
access the extended configuration space of the bridge by using type-0 configuration cycles.
The A-side bridge can also be accessed by type-1 configuration cycles, but the primary bus number
of the bridge must be tracked. On power-up, before the configuration retry bit is cleared, it is zero.
When this technique is used, the AD24 and AD25 can be used for public or private devices based
on BINIT[4], and AD26 and AD27 can be used for public devices.
No
Retry Disable Sequence
The 80333 has three integrated units (A-bridge, B-bridge, and ATU) that include retry bits, and
these must be disabled in a specific sequence. When the retry bit is set, the PCI interface responds
to all type-0 configuration cycles with a retry transaction. When the retry bit is cleared, type-0
transactions are completed normally. The default condition of the retry bit is determined by the
RETRY reset strap muxed on AD[6].
without resetting the bridge registers, the bridge retry release sequence MUST NOT be executed if
the bridge retry bit is not set. Code can check the A segment BINIT register (bit 3) to determine if
the bridge retry bits need to be cleared or not.
Proper retry disable sequence as initiated by the Intel XScale
1. Set the Bus Master Enable bit for the ATU in ATUCMD[2] (offset 04h) and enable the
2. Read A segment BINIT to determine if bridge is currently retrying type 0 config cycles.
3. If the bridge is retrying cycles (read A-bridge BINIT register and check if bit 3 is set):
Fix. See the
Fix. See the
outbound ATU in the ATUCR.
b. Read the primary bus number from the A-bridge for use in creating the type 1 transaction
d. Implement any errata workarounds that require bridge configuration cycle setup.
a. Set the Bus Master Enable bit for the A-bridge in PCICMD[2] (offset 04h).
c. Enable the bridge (A side at a minimum, B side if application requires) to pass config
e. Clear the B-bridge retry bit in BINIT[3] (offset FCh using a type 1 transaction as defined
to the B side.
retry cycles upstream by setting bit 15 in the PCI Express Device Control Register register
at offset 0x4c.
in the PCI specification).
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
®
7.
7.
processor:
Specification Update
®
®
processor can
processor)
®
processor