QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 16

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Non-Core Errata
7.
Problem:
Implication:
Workaround:
Status:
8.
Problem:
Implication:
Workaround:
Status:
16
Auto-Refresh command also generates a Precharge All command on
DDR bus
When an auto-refresh command is issued to the MCU SDRAM Initialization Register (write 0x6 to
SDIR), the hardware state machine executes a Precharge All command and then an Auto-Refresh
command.
Some DIMMs might fail to initialize.
There is no way to decouple the Precharge All and Auto-Refresh commands in the MCU.
However, the DCAL can issue an Auto-Refresh command, which can be used instead to issue the
Auto Refresh for initialization.
For both DDRI and DDRII initialization sequences, there are two back-to-back Auto-Refresh
(ARF) commands issued to the DIMM (accomplished by writing 0x6 to MCU_SDIR
0xFFFF_E500 twice). This sequence is replaced by writing to the DCAL Control and Status
Register (DCALSR) 0xFFFF_F500 to issue an Auto-Refresh to each Chip Select; thus, there are
four writes to the DCALSR as opposed to the previous two writes to MCU_SDIR. The exact
address and data values are as follows:
ADDRESS
0xFFFF_F500
0xFFFF_F500
0xFFFF_F500
0xFFFF_F500
No
Coalesced writes to 32-bit memory can cause data corruption
The Bus Interface Unit (BIU) can cause data corruption within the memory controller unit when
either an 8-byte write with a starting address offset of four (that is, Dword alignment) or a 12-byte
write is done to 32-bit memory (or the 32-bit memory region).
This issue can cause data corruption. This is not an issue with 64-bit memory subsystems.
When the use of 32-bit memory or the 32-bit memory region is required, write coalescing must be
turned off.
No
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
WRITE_DATA
0x8000_0001
0x8000_0001
0x8010_0001
0x8010_0001
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
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NOTE
ARF to CS[0]
ARF to CS[0]
ARF to CS[1]
ARF to CS[1]
Specification Update
7.
7.