QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 20

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Non-Core Errata
Status:
19.
Problem:
Implication:
Workaround:
Status:
20.
Problem:
Implication:
Workaround:
Status:
20
Note: When error escalation is not properly enabled in the MCH/root complex, there can be a potential
race condition between the completion being returned to the CPU and the error escalation. Read
completion might complete normally at the CPU followed by error escalation as an
Interrupt/SERR.
No
ATU claims PCI commands 8 and 9 when issued as Dual Address Cycle
(DAC)
In PCI mode, commands 8 and 9 are reserved. The appropriate PCI response to these commands is
to master abort. When these commands are issued as a Dual Address Cycle (DAC), the Address
Translation Unit (ATU) claims them, and they are executed as Memory Read (command 8) and
Memory Write (command 9) on the internal bus. The ATU properly master aborts SAC PCI
commands 8 and 9.
This issue does not occur in PCI-X mode.
No negative impact is expected, since these PCI commands are “reserved” and are never normally
issued to the ATU.
None
No
Failure to train down in presence of degraded lane
During the PCI Express* training sequence, when a broken endpoint has correct receiver
termination on a lane and transmits training sequences on the lane which are invalid, the 80333
fails to link train.
The PCI Express* specification intends that, when some lanes are transmitting invalid data instead
of valid training sequences, those lanes must be treated as broken, and the link must fail down to an
acceptable width, such as ×1. When Lane 0 is failing in this manner, the PCI Express*
specification anticipates that the link would fail to train. When a higher-numbered lane is failing in
this manner, the PCI Express* specification requires that the link attempt to train as ×1 on lane 0.
In either case, the 80333 does not train for the problem scenario.
On production material, failures are anticipated to be either a broken transmitter path or a broken
receiver path, or a silent transmitter. The 80333 trains properly for these failure modes, since either
the receiver termination is missing, or the transmitted signals are not seen at the 80333. In order to
see invalid transmitted data on lanes at the 80333, either a logic bug in the other PCI Express*
endpoint is required, or a signal integrity issue so severe as to make operation impossible, such as a
broken or intermittent connection.
None. A non-compliant or broken device can exhibit this erratum.
No
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Specification Update
7.
7.
7.