QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 23

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

27.
Problem:
Implication:
Workaround:
Status:
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Problem:
Implication:
Workaround:
Status:
29.
Problem:
Implication:
Workaround:
Status:
Specification Update
SERR fatal/non-fatal error message enabled with incorrect error message
enabled bit
When the SERR# Enable (SEE) bit in the PCI Command Register (offset 0x4) is not set, then in the
Advanced Error Reporting scheme when SERR is configured as a fatal error, the generation of a
SERR fatal error message is mistakenly gated by the Non-Fatal Error Reporting Enabled bit
(bit[1]) instead of the Fatal Error Reporting enabled bit (bit[2]) of the Device Control Register
(offset 4Ch). Likewise, when SERR is configured as a non-fatal error, the generation of a SERR
non-fatal error message is gated by the Fatal Error Reporting enabled bit.
The SERR fatal error message can be generated only when non-fatal error messaging is enabled,
and vice-versa.
Set both Fatal and Non-Fatal Error Reporting Enabled bits, and mask errors individually via
Uncorrectable PCI-X Error Mask Register (offset 130h) when escalation of these errors is not
desired.
No
Configuration write to offset 70h of A- and B-bridge (PM_CSR - PCI Express
Power Management Control/Status Register) using non-continous byte
enables does not capture the data value
A configuration write to single-byte offset 71h of the A-bridge and B-bridge configuration space
does not capture the data value written to it. Specifically, performing this configuration write to
offset 70h with byte enables of 2h, 6h, or Ah in order to write to offset 71h does not work.
Register offset 70h is the PCI Express* Power Management Control/Status Register (PM_CSR).
The byte at location 71h contains the PME enable bit (bit[8] of 70h) and PME status bit (bit[15] of
70h). The above mechanism does not work to either set or clear the PME enable bit, or to clear the
PME status bit.
Write to offset 71h by performing a word (byte enable 3h) or a dword (byte enable Fh) to offset
70h.
No
The 80333 might become unresponsive when transitioning into the D3
power state
When the 80333 is transitioned to a power state of D3 or lower, the 80333 device might become
unresponsive.
There have been no observed failures on systems with currently available software. Operating
systems that independently manage the power state of the 80333, outside the scope of system-level
power state transitions, might result in the loss of link communications to the MCH.
Independent device power-state management of the 80333 must be avoided. If the 80333 becomes
unresponsive, a fundamental device reset must be asserted to return the system to normal
operation.
No
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Intel® 80333 I/O Processor
7.
7.
7.
Non-Core Errata
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