QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet
QG80333M500 S L9BH
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QG80333M500 S L9BH Summary of contents
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... Intel® 80333 I/O Processor Specification Update April 2006 The Intel® 80333 I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are doc- umented in this specification update. Order Number: 305435-011US ...
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... Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. ...
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Contents Contents Revision History ......................................................................................... 5 Preface ....................................................................................................... 6 Summary Table of Changes ....................................................................... 7 Identification Information .......................................................................... 13 Non-Core Errata ....................................................................................... 14 Core Errata............................................................................................... 27 Specification Changes.............................................................................. 31 Specification Clarifications........................................................................ 33 Documentation Changes .......................................................................... 48 3 ...
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Revision History Date Version Added: • A-1 stepping information to all Summary tables and to • Status change of Erratum April 2006 011 • Status change of Specification Change • Status change of Specification Clarification • Documentation Change Added: February ...
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... Intel 6700PXH 64-bit PCI Hub Specification Update Nomenclature Errata are design defects or errors. These may cause the behavior of the Intel® 80333 I/O 1 Processor (80333) to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices ...
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... Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel® 80333 I/O Processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted ...
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... Intel® 80333 I/O Processor Summary Table of Changes Non-Core Errata (Sheet Stepping No. Page Status A-0 A Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix Fix ...
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... Recommended DLL register values Doc DDR-II JEDEC initialization sequence includes writes to EMRS2 and EMRS3 Doc REFCLK relationship to voltage rails Doc Case temperature (Tcase) change Doc PWRGD and RSTIN# sequencing Fixed Internal Clock Misalignment. Intel® 80333 I/O Processor Summary Table of Changes Errata Errata 9 ...
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... No Fix UART Interrupt Identification Register No Fix Reads on 16-bit PBI bus operate as 32-bit No Fix 3 1.5 V leakage Accessing extended bridge configuration space from the Intel XScale® No Fix processor Recommended B-segment termination when using the 80333 on PCI Express* No Fix adapter cards B-segment arbiter might not park on the last master when in PCI-X 133 MHz ...
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... DMA transactions from local memory to a conventional PCI target can complete out of order SBR1 Programming with Bank 1 Unpopulated 32-bit Writes to Unaligned 64-bit Addresses are Promoted to 64-bit Aligned Writes ATU Retry Response Through the Bridge Fixed Case Temperature Clarification. Intel® 80333 I/O Processor Summary Table of Changes 11 ...
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... Intel® 80333 I/O Processor Summary Table of Changes Documentation Changes No. Document Revision 1 305433-001 2 305433-002 3 305432-001 4 305433-003 12 Page Status Documentation Changes 48 Doc PCI clock timings table missing note 48 Doc Wrong Voltage Values in Table 23 48 Doc SBR1 Programming When Bank 1 is Unpopulated 48 Doc ...
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... QG80333M500 SL9BH SL9BB NQ80333M667 QG80333M667 SL9BJ SL9BC NQ80333M800 QG80333M800 SL9BK Processor Device ID 0x69054210 0x69054210 Intel® 80333 I/O Processor Identification Information Processor Speed Notes (MHz) Engineering Samples 500 PB-free Eng Samples Engineering Samples 667 PB-free Eng Samples Engineering Samples 800 PB-free Eng Samples ...
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... Intel® 80333 I/O Processor Non-Core Errata Non-Core Errata 1. CAS latency of three not supported for DDR-II On-Die Termination (ODT) Problem: For DDR-II memory with a CAS Latency (CL) of three, the memory controller unit (MCU) does not provide the proper timing for the On-Die Termination signals (ODT[1:0]). The JEDEC DDR-II SDRAM Specification, September 2002 states that ODT must be driven one cycle prior to the write command, but the MCU does not meet this timing ...
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... Workaround: Intel can provide two BSDL files which allow opens and shorts testing, as long as it does not test the ID and BYPASS instructions. One BSDL file covers the Intel XScale other BSDL file covers the I/O processor, with the exception that both instruction sets are reduced from since they are operating independently ...
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... Intel® 80333 I/O Processor Non-Core Errata 7. Auto-Refresh command also generates a Precharge All command on DDR bus Problem: When an auto-refresh command is issued to the MCU SDRAM Initialization Register (write 0x6 to SDIR), the hardware state machine executes a Precharge All command and then an Auto-Refresh command. ...
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... PCI initialization pattern. Another workaround is to bring up 3.3 V and 1.5 V power rails simultaneously, but continue to maintain the power-sequencing requirements (as specified in the Intel® 80333 I/O Processor Design Guide) for these two power rails. Status: No Fix ...
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... Intel® 80333 I/O Processor Non-Core Errata 11. VPD Data Register bit[19] is not read/write Problem: VPD (Vital Product Data extended capability of the ATU. Bit[19] of the VPD Data Register (FFFF_E1BCh) is implemented as RC (read clear) instead of RW (read/write). Implication: This is application-dependent, as VPD provides the system with information that uniquely identifies hardware and, potentially, software elements of a system ...
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... Uncorrectable error escalation must be enabled in the MCH and the 80333 to contain this data parity escape. Therefore, a complete workaround for this erratum also includes MCH/root complex specific BIOS updates. Refer to the latest version of the Intel Specification Update for details on this workaround. Specification Update Intel® ...
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... Intel® 80333 I/O Processor Non-Core Errata Note: When error escalation is not properly enabled in the MCH/root complex, there can be a potential race condition between the completion being returned to the CPU and the error escalation. Read completion might complete normally at the CPU followed by error escalation as an Interrupt/SERR ...
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... This bit can be reprogrammed to match the specified default value when desired. BIOS or firmware must set register 10Ch bit[13 for both A- and B-segments. For accessing extended bridge configuration space from the Intel XScale “Accessing extended bridge configuration space from the Intel XScale® processor” on page Status: No Fix ...
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... Intel® 80333 I/O Processor Non-Core Errata 24. Performance across an upstream ×1 PCI Express* link is less than expected Problem: When the 80333 is configured with an upstream ×1 PCI Express* link, the realized performance is significantly less than the predicted linear assumption that a x1 link provides 1/4 the performance link ...
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... Status: No Fix. Not to be fixed. See the Specification Update Intel® 80333 I/O Processor Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page Non-Core Errata 7. ...
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... PCI bus after translation. Refer to Section 3.2.2 “Outbound Transactions – Single Address Cycle (SAC) Internal Bus Transactions” in the Intel® 80333 I/O Processor Developer’s Manual for more information on how the windowing and translation scheme works. ...
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... Not to be fixed. The BIOS/firmware workaround must be left in place for all 80333 steppings. See the Table , “Summary Table of Changes” on page Specification Update Intel® 80333 I/O Processor Table , “Summary Table of Changes” on page Table , “Summary Table of Changes” on page 7. Non-Core Errata 7 ...
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... SDRAM. Subsequent warm or cold resets may clear the condition and allow the 80333 to continue operation. Workaround: In most cases, doing a cold or warm reset will clear this condition. Increasing the 1.5v power supply will reduce the probability of a processor hang. Intel is screening parts to eliminate the probability of occurrence (refer to page 32). ...
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... For this shared memory region, mark it as write-through memory in the core page table. This prevents the data from ever being written out as dirty. Status: No Fix. See the Table , “Summary Table of Changes” on page Specification Update Intel® 80333 I/O Processor Core Errata ...
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... Intel® 80333 I/O Processor Core Errata 3. Performance Monitor Unit event 0x1 can be incremented erroneously by unrelated events Event 0x1 in the Performance Monitor Unit (PMU) can be used to count cycles in which the instruction cache cannot deliver an instruction. The only cycles counted are supposed to be those due to an instruction cache miss or an instruction TLB miss ...
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... MMU, caches mrc p15, 0, r0, c2, c0 CPWAIT mov r0, r0 sub pc, pc, #4 Status: No Fix. See the Table , “Summary Table of Changes” on page Specification Update Intel® 80333 I/O Processor Core Errata ...
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... Problem: The IEEE 1149.1 specification states that the effects of updating all parallel JTAG registers are expected to be seen on the falling edge of TCK in the Update-DR state. The Intel XScale processor parallel JTAG registers incorrectly require an extra TCK rising edge to make the update visible ...
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... DQS being late in the data eye, which could lead to ECC errors. Errors have only been observed when using DIMMs that have a low DQS duty cycle. Note: All of the Intel validation up to this point has been with the default, worst case DLL values and all DIMMs used in validation have passed. ...
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... Due to non-core Erratum 35, Internal Clock Misalignment Can Cause Processor Hang, on page Intel is screening parts to eliminate the probability of occurrence. Until this is fixed in a future stepping, a screen has been implemented which will screen out parts exhibiting this issue with a VCC15 greater than 1.46v. ...
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... Fix. See the Table , “Summary Table of Changes” on page and 2 GB DDR333 capacities not tested in post-silicon validation Issue: Intel is not able to test 64 MB and 2 GB DDR333 DIMMs due to availability. Intel cannot guarantee proper functionality since validation cannot be completed. Status: No Fix. See the Table , “ ...
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... The default condition of the retry bit is determined by the RETRY reset strap muxed on AD[6]. Note: Since a PCIX reset independent of a PCIE reset will result in a reset of the Intel XScale without resetting the bridge registers, the bridge retry release sequence MUST NOT be executed if the bridge retry bit is not set ...
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... Therefore read case two interrupts is generated. When the interrupt source is masked, then only the master abort on reads is detected, and this is from the direct core error. Status: No Fix. See the Table , “Summary Table of Changes” on page Specification Update Intel® 80333 I/O Processor Specification Clarifications ...
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... There is a slight lag in the time it takes between clearing a status bit inside the unit and the corresponding bit in the Interrupt Controller Unit Status Register getting cleared. This has the potential of generating a false interrupt, meaning that the Intel XScale but the handler is not able to find any source reported in the ICU registers. This condition can be avoided by adding a read from any ICU register, after the bit is cleared in the local unit before returning from the interrupt handler ...
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... HPRST (change frequency) [Note: this is a software step. Bus reset happens automatically due to the change frequency.] …operating… 7. HPRST# 1 -> 0 (SW slot disable) …off/removal… …new card inserted… step 2 Status: No Fix. See the Table , “Summary Table of Changes” on page Specification Update Intel® 80333 I/O Processor Specification Clarifications 7. 37 ...
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... The Core Bus Interface Unit orders transactions based on PCI rules. This allows outgoing writes to pass incoming reads. For most devices on the internal bus, this does not cause problems since the devices function asynchronously with respect to each other. For transactions between the Intel ® ...
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... Two-byte and four-byte read transactions on the Peripheral Bus Interface (PBI) bus operate as burst reads (in other words, two 16-bit read cycles). All the read transactions from the Intel XScale processor to PBI devices (such as SRAM, flash, and so on) are translated to burst reads with burst size of 2, even though there is no necessity to generate a burst transaction ...
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... Intel® 80333 I/O Processor Specification Clarifications 23. Accessing extended bridge configuration space from the Intel XScale processor Issue: In certain cases, the Intel XScale of the bridge headers (for example, see Non-Core Erratum 22, PCI Express* Flow Control Protocol Error Severity bit” on page processor issues the configuration cycle address using OCCAR, bits[27:24] can be used for addressing the extended space ...
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... For motherboard designs assumed that the SMBus is routed only to devices that are required and that remain powered. Status: No Fix. See the Table , “Summary Table of Changes” on page Specification Update Intel® 80333 I/O Processor Specification Clarifications ...
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... Intel® 80333 I/O Processor Specification Clarifications 30. PBI lockout condition Issue: When the core tight loop writing to the PBI bus, while the DMA is doing a large block transfer (for example, from SRAM, located on the PBI, to DDR memory), the DMA can be locked out of accessing the PBI and the transaction will never complete. ...
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... PME request from the PCI-X slot. Status: No Fix. See the Table , “Summary Table of Changes” on page Specification Update Intel® 80333 I/O Processor Specification Clarifications 7. 16 (“Unreliable PCI Express* link 7. “OCD and Receive Enable calibration de-featured” ...
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... Note: This affects PCI mode exclusively, and is not an issue when the secondary busses are operating in PCI-X mode. Whether corruption can occur through this mechanism is dependent upon the behavior of the non-Intel® MCH component. If the MCH in use behaves similarly to Intel® MCH designs, there is no exposure to data corruption, and the incomplete completion match does not have any side effects ...
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... Therefore, when using DDR-I memory the RCVDLY default setting of 5, may need to be changed operate correctly with a specific DIMM based on the board layout. For example, the Redboot reference code provided by Intel uses a value order to allow for a wider compatibility with various DIMMs. ...
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... ODT (On Die Termination) signals (ODT[1:0]) which are used with DDR-II DIMMs to turn on termination during writes. Section 8.7.6 in the Intel® 80333 I/O Processor Developer’s Manual (305432) states, “If bank 1 is unpopulated, SBR1[6:0] is programmed either with all zeroes or a value equal to SBR0[6:0].” To clarify this statement for single-banked DDR-II DIMMs, if bank 1 is unpopulated, then the entire SBR1 must be programmed the same as SBR0 ...
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... Internal models indicate that certain elevated case temperatures (Tcase) of the Intel® 80333 I/O processor may cause elevated field failures in later years of operation. This clarification is precautionary, as Intel has not seen any failures of the 80333 products in the field. Internal modeling data indicates that the degree of failure risk decreases with lower operating frequency (i.e. – ...
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... SBR0[6:0].” Workaround: The sentence should be changed to “If bank 1 is unpopulated, SBR1[6:0] and SBR1[31:30] should be programmed with a value equal to SBR0[6:0] and SBR0[31:30].” Affected Docs: Intel® 80333 I/O Processor Developer’s Manual (305432-001) 4. PCI Express clock cycle time minimum Issue: Table 27 in the 80333 datasheet shows the PCI Express clock cycle time, Tc2, as 10ns minimum ...