QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 41

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Specification Update
Note: AAU source reads from PCI are not supported; only local memory can be used for this.
Power plane isolation for Battery Back-Up (BBU) mode
During battery back-up (BBU) mode, when the battery powers the DIMM and the VCC25/18
signals (1.8 V or 2.5 V, depending on the memory type being used) on a single power plane, the
battery life will probably be reduced due to leakage.
To attain longer battery life, the DIMM and VCC25/18 power planes must be isolated. The power
plane isolation can be accomplished by using a FET.
No
AAU result can be written directly to PCI host memory
The Application Accelerator Unit (AAU) can write results not only to local memory but also to the
PCI bus host memory via the ATU.
This feature can be applied to degraded RAID-5 reads, where the AAU result is the reconstructed
data for the host I/O read. The AAU can write its result to PCI; therefore, the degraded read XOR
result can be written directly to host memory. This eliminates the need for a DMA operation to
transfer the result from local memory to host memory via PCI.
Savings for the RAID application include the following:
No
SMBus connection recommendations for PCI Express* adapter cards
PCI Express* cards based on the 80333 must implement the SMBus signals in one of the following
ways:
For motherboard designs, it is assumed that the SMBus is routed only to devices that are required
and that remain powered.
No
1. The SMDAT and SMCLK signals from the PCI Express* connector must be left as “no
2. When the SMBus feature is required, an isolation device (for example, the LTC4301) must be
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•
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Fix. See the
Fix. See the
Fix. See the
No DMA descriptor needs to be generated.
No DMA interrupt needs to be serviced.
Memory and internal bus bandwidth is saved (result write by AAU and read by DMA).
Read I/O is serviced faster (eliminates latency of DMA operation).
connects”. The SCLK and SDTA signals on the 80333 must have pull-ups even when they are
not used. The pull-ups prevent the inputs from oscillating and potentially causing other
problems.
placed between the SMBus signals on the PCI Express* connector and the 80333, so that the
system has no connection to the 80333 on these two signals when power is off.
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
7.
7.
7.
Specification Clarifications
Intel® 80333 I/O Processor
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