QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 25

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Problem:
Implication:
Workaround:
Status:
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Problem:
Implication:
Workaround:
Status:
34.
Problem:
Implication:
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Status:
Specification Update
I2C Control Register reset bit does not function
The I2C Control Register (ICR0 and ICR1) bit 14 is supposed to be used for resetting the I2C unit,
but writing a '1' to this bit does not reset the I2C unit. Writing a '1' to bit 14 has no effect.
The I2C unit cannot be reset by using ICRx.14.
Depends on what needs to be accomplished. Asserting P_RST# or setting BCR.6 will reset the I2C
unit but will also reset the entire chip or the secondary bus/ATU. For an I2C bus lock condition, it
may be cleared by software doing a toggle of the GPOD[11:10] to toggle SCL[1:0]. If SDA[1:0]
need to be toggled, then an external device or unused GPIO will need to be used to control this
sequence.
No
MSI Hot-Plug Interrupt issue
An MSI generated by the standard hot-plug controller may get corrupted in the presence of another
ACPI hot-plug driver. The ACPI driver performs configuration reads of DWSEL/DWORD
register in order to determine the hot-plug capability of all the ACPI devices. If the MSI is
generated by the Standard Hot-Plug Controller (SHPC) in this time period, there is a possibility of
the MSI getting corrupted. As a result the MSI may not get issued upstream to the MCH. The
above is a result of interaction of separate events that are unpredictable.
With the above condition described, the hot-plug device may not get recognized by the OS.
Currently this issue is susceptible to only MSI aware systems.
Disable 80333 SHPC MSI. By default MSI_MC (Offset 5Eh, function 2 only) bit 0 MSI Enable is
clear. BIOS/FW must keep this default value.
No
Under certain conditions, inbound prefetched PCI read requests may return
wrong data to the requestor
With some prefetch policy settings, the 80333 may over-aggressively prefetch data for PCI reads
and subsequently return the wrong data to the requestor. This problem only exists when there is
more than one active agent on the PCI bus. This problem exists for all supported frequencies. This
problem exists on both 80333 PCI segments. This problem does not affect PCI-X operation at any
supported frequency.
Inbound read requests that are enabled for prefetching may return invalid data when multiple
agents exist on the same PCI bus. No error is reported by the 80333.
BIOS or firmware must set D0:F0/F2 Offset 184h (Dword) bit [2] to 1. The workaround corrects
the problem at all supported frequencies and all prefetch policy settings.
No Fix
steppings. See the
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
Not to be fixed. The BIOS/firmware workaround must be left in place for all 80333
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
7.
Intel® 80333 I/O Processor
7.
7.
Non-Core Errata
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