QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 11

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Specification Clarifications (Sheet 2 of 2)
Specification Update
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Status
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Fixed
OCD and Receive Enable calibration de-featured
PWRDELAY needs only a pull-up for battery back-up mode
PCI Express* L0s functionality not supported in the 80333
DDRRES2 can be pulled down to reduce current during self-refresh
DDRSLWCRES resistor values
B_PME# routing recommendation when using Parallel Hot Plug 1-slot, no-glue
mode
Multi-Transaction Timer grants fewer clocks in PCI mode than expected
Byte Enables (BE) not included in PCI delayed reads can cause data corruption
Interleaving AAU descriptors
RCVDLY setting for DDR-I memory
Embedded Usage Models
ATUBAR3 Functionality
VREF isolation for Battery Back-up (BBU) mode
I2C Unit Enabling
DMA transactions from local memory to a conventional PCI target can
complete out of order
SBR1 Programming with Bank 1 Unpopulated
32-bit Writes to Unaligned 64-bit Addresses are Promoted to 64-bit Aligned
Writes
ATU Retry Response Through the Bridge
Case Temperature
Clarification.
Specification Clarifications
Summary Table of Changes
Intel® 80333 I/O Processor
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