QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 14

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Non-Core Errata
Non-Core Errata
1.
Problem:
Implication:
Workaround:
Status:
2.
Problem:
Implication:
Workaround:
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3.
Problem:
Implication:
Workaround:
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14
CAS latency of three not supported for DDR-II On-Die Termination (ODT)
For DDR-II memory with a CAS Latency (CL) of three, the memory controller unit (MCU) does
not provide the proper timing for the On-Die Termination signals (ODT[1:0]). The JEDEC DDR-II
SDRAM Specification, September 2002 states that ODT must be driven one cycle prior to the write
command, but the MCU does not meet this timing.
CAS latency of three is not supported in the 80333; therefore, there is minimal performance impact
as compared to CAS latency of four.
Use CAS latency = 4 or do not use the ODT feature.
No
Legacy power fail mechanism does not work
For previous I/O processor generations, an external clock was required to maintain the incoming
PCI clock (P_CLK) long enough for the power-fail sequence to be sent to the memory. This is what
is referred to as “legacy power fail.” The internal control circuit that enables the legacy power-fail
method is broken.
Legacy power-fail cannot be used.
For the 80333, a new feature was added which keeps internal clocks running on power fail.
No
A_REQ64# and B_REQ64# initialization pattern timing violation in PCI-33
mode
The PCI Local Bus Specification, Revision 2.3 states RST# to REQ64# hold time is 0 ns minimum
and 50 ns maximum (Trrh). The 80333 drives the REQ64# signal for three cycles after RST#
deasserts. Therefore, in PCI-33 mode, this is 90 ns, which violates the 50 ns maximum.
All other PCI and PCI-X modes are within the PCI Local Bus Specification, Revision 2.3 (that is,
PCI-66 is 45 ns).
No negative impact expected.
There is no overlap between the 80333 assertion of REQ64# for the initialization sequence, and the
first assertion of FRAME#. As per the PCI Local Bus Specification, Revision 2.3, Trhff defines the
minimum time from RST# high to first FRAME# assertion as 5 clocks. Since the 80333 deasserts
REQ64# at three clocks following RST# high, there is no overlap with FRAME# being asserted as
it is not allowed to be asserted any sooner than five clocks.
No
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
Fix. Not to be fixed. See the
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Specification Update
7.
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7.