QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 38

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Specification Clarifications
18.
Issue:
38
Bus Interface Unit follows PCI ordering rules
The Core Bus Interface Unit orders transactions based on PCI rules. This allows outgoing writes to
pass incoming reads. For most devices on the internal bus, this does not cause problems since the
devices function asynchronously with respect to each other. For transactions between the Intel
XScale
example:
This code can potentially load the register r3 with the value 0x55555555, since the store in line 6
might pass the load in line 5. This happens only with uncached transactions on the internal bus.
The MCU core port enforces strict ordering and does not exhibit this behavior. When the MCU
core port is used, this issue does not occur.
When caching is enabled, the initial read initiates a cache-line fill. The subsequent write is pended
in the Intel XScale
issue does not occur.
When caching is disabled, and the caching policy is stall-until-complete (X = 0, C = 0, B = 0), this
issue does not occur. For other MMU settings with caching disabled, the issue can occur.
Specifically regions with data cache and write buffer policies of bufferable (X = 0, C = 0, B = 1) or
coalescing-disabled-bufferable (X = 1, C = 0, B = 1) are vulnerable to this issue. In addition,
regions configured as write through (X = 0, C = 1, B = 0) are also vulnerable to this issue.
In addition, when caching is enabled in the MMU page tables, but the DCache is disabled in the
CP15 ARM Control Register, then the effective caching policy is bufferable and this reordering
must be accounted for.
It is important to realize that any code that accesses memory spaces on the internal bus must
account for this possibility. Code that dynamically disables cache (for example, Flash
programming routines) must ensure that the caching policy for the appropriate memory region is
set to “stall until complete” until the cache is re-enabled.
The simplest scenario to reproduce is a pair of back-to-back function calls, for example:
0: ldr r0, =0x40000
1: ldr r1, =0xaaaaaaaa
2: ldr r2, =0x55555555
3: str r1, [r0]
4: … <time-delay to allow the previous transactions to complete>
5: ldr r3, [r0]
6: str r2, [r0]
main:
fun1:
fun2:
®
bl
bl
…
…
…
stmfd
ldmfd
stmfd
processor and memory via the internal bus, this can result in unexpected data. For
fun1
fun2
sp!,{r4, r5, r6, r7, r8, r9, r10, lr}
sp!,{r4, r5, r6, r7, r8, r9, r10, pc}
sp!,{r4, fp, ip, lr}
®
processor until the line fill and the ldr instruction complete. In this case, this
Specification Update