QG80333M500 S L9BH Intel, QG80333M500 S L9BH Datasheet - Page 42

• Manufacturer Part Number: QG80333M500 S L9BH
• Manufacturer: Intel

Specifications of QG80333M500 S L9BH

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Intel® 80333 I/O Processor
Specification Clarifications
30.
Issue:
Status:
31.
Issue:
Status:
32.
Issue:
Status:
33.
Issue:
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34.
Issue:
Status:
42
PBI lockout condition
When the core is in a tight loop writing to the PBI bus, while the DMA is doing a large block
transfer (for example, from SRAM, located on the PBI, to DDR memory), the DMA can be locked
out of accessing the PBI and the transaction will never complete.
If this condition occurs, use one of these workarounds:
No
PFREQ functionality
The PFREQ bits (BCNF[10:9], offset 40h) cannot be used to change the actual PCI bus frequency.
The only way to change the PCI bus frequency is to reset the bus or use the hot-plug controller.
Note that this is an artifact of specification clarification
same mechanism that requires two resets with the hot-plug controller, prevents the 33 MHz to/from
66 MHz PCI transition without hot plug. Other transitions (such as PCI-X) do work correctly; it is
only the PCI33 that cannot change to or from another bus speed.
No
PWRDELAY functionality during power sequencing
When the 3.3 V rail is powered on and the 1.5 V rail is powered off, the PWRDELAY input signal
drives out until the 1.5 V rail powers up. This is important to understand if still using the legacy
power-fail circuit, because it might cause other circuitry to function incorrectly. The proper usage
of PWRDELAY is described in Specification Clarification
for battery back-up mode” on page
circuitry and tied to a 1.5 KΩ pull-up resistor.
No
HPI# (High Priority Interrupt) is a maskable interrupt
The HPI# interrupt input is both maskable and masked by default (as are all interrupts). It is
controlled by INTCTL1[31]. HPI# operates the same as the other external interrupt inputs
(XINT[7:0]#).
No
OCD and Receive Enable calibration de-featured
The ability to adjust the electrical interface to account for out-of-specification DDR-II DIMMs
using OCD (off-chip driver) and receive enable calibration, is no longer a supported feature.
No
1. Change the MTTR1 from 98h (default) to a lower value (such as 01h). A lower value allows
2. Add a core read along with the core write, causing it stall and preventing it from starving the
3. Add NOPs or dummy instructions to ensure the loop spans greater than two cache lines.
4. Modify the loop such that the write is not done on every iteration.
Fix. See the
Fix. See the
Fix. See the
Fix. See the
Fix. See the
the DMA (or ATU which can also master a transaction to the PBI) to gain access to the PBI,
because the BIU is given shorter access for back-to-back BIU internal bus transactions.
DMA.
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
Table , “Summary Table of Changes” on page
43), which recommends that PWRDELAY be isolated from all
17 (“SHPC sequence” on page
35 (“PWRDELAY needs only a pull-up
7.
7.
7.
7.
7.
Specification Update
37). The