MC9S08GB60ACFUE Freescale, MC9S08GB60ACFUE Datasheet - Page 93

• Manufacturer Part Number: MC9S08GB60ACFUE
• Manufacturer: Freescale

Specifications of MC9S08GB60ACFUE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

6.6.3
Port C includes eight general-purpose I/O pins that share with the SCI2 and IIC modules. Port C pins used
as general-purpose I/O pins are controlled by the port C data (PTCD), data direction (PTCDD), pullup
enable (PTCPE), and slew rate control (PTCSE) registers.
If the SCI2 takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to
provide slew rate on the SCI2 transmit pin, TxD2. PTCPE can be used, provided the corresponding
PTCDD bit is 0, to provide a pullup device on the SCI2 receive pin, RxD2.
If the IIC takes control of a port C pin, the corresponding PTCDD bit is ignored. PTCSE can be used to
provide slew rate on the IIC serial data pin (SDA1), when in output mode and the IIC clock pin (SCL1).
PTCPE can be used, provided the corresponding PTCDD bit is 0, to provide a pullup device on the IIC
serial data pin, when in receive mode.
Reads of PTCD will return the logic value of the corresponding pin, provided PTCDD is 0.
Freescale Semiconductor
PTCD[7:0]
Reset
Field
7:0
W
R
PTCD7
Port C Registers (PTCD, PTCPE, PTCSE, and PTCDD)
Port C Data Register Bits— For port C pins that are inputs, reads return the logic level on the pin. For port C
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
0
7
PTCD6
0
6
Figure 6-17. Port C Data Register (PTCD)
PTCD5
Table 6-9. PTCD Field Descriptions
MC9S08GB60A Data Sheet, Rev. 2
0
5
PTCD4
0
4
Description
PTCD3
3
0
PTCD2
0
2
Chapter 6 Parallel Input/Output
PTCD1
0
1
PTCD0
0
0
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