MC9S08GB60ACFUE Freescale, MC9S08GB60ACFUE Datasheet - Page 100

• Manufacturer Part Number: MC9S08GB60ACFUE
• Manufacturer: Freescale

Specifications of MC9S08GB60ACFUE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Chapter 6 Parallel Input/Output
6.6.7
Port G includes eight general-purpose I/O pins that are shared with BKGD/MS function and the oscillator
or external clock pins. Port G pins used as general-purpose I/O pins are controlled by the port G data
(PTGD), data direction (PTGDD), pullup enable (PTGPE), and slew rate control (PTGSE) registers.
Port pin PTG0, while in reset, defaults to the BKGD/MS pin. After the MCU is out of reset, PTG0 can be
configured to be a general-purpose output pin. When BKGD/MS takes control of PTG0, the corresponding
PTGDD, PTGPE, and PTGPSE bits are ignored.
Port pins PTG1 and PTG2 can be configured to be oscillator or external clock pins. When the oscillator
takes control of a port G pin, the corresponding PTGD, PTGDD, PTGSE, and PTGPE bits are ignored.
Reads of PTGD will return the logic value of the corresponding pin, provided PTGDD is 0.
100
PTFDD[7:0]
PTFSE[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTFDD7
PTFSE7
Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD)
Slew Rate Control Enable for Port F Bits — For port F pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port F pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
Data Direction for Port F Bits — These read/write bits control the direction of port F pins and what is read for
PTFD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port F bit n and PTFD reads return the contents of PTFDn.
0
0
7
7
PTFDD6
PTFSE6
Figure 6-31. Slew Rate Control Enable for Port F (PTFSE)
0
0
6
6
Figure 6-32. Data Direction for Port F (PTFDD)
Table 6-24. PTFDD Field Descriptions
Table 6-23. PTFSE Field Descriptions
PTFSE5
PTFDD5
MC9S08GB60A Data Sheet, Rev. 2
0
0
5
5
PTFDD4
PTFSE4
0
0
4
4
Description
Description
PTFDD3
PTFSE3
3
0
3
0
PTFDD2
PTFSE2
0
0
2
2
PTFDD1
PTFSE1
Freescale Semiconductor
0
0
1
1
PTFDD0
PTFSE0
0
0
0
0