MC9S08GB60ACFUE Freescale, MC9S08GB60ACFUE Datasheet - Page 153

• Manufacturer Part Number: MC9S08GB60ACFUE
• Manufacturer: Freescale

Specifications of MC9S08GB60ACFUE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

9.3.2
9.4
9.4.1
The KBIPEn control bits in the KBI1PE register allow a user to enable (KBIPEn = 1) any combination of
KBI-related port pins to be connected to the KBI module. Pins corresponding to 0s in KBI1PE are
general-purpose I/O pins that are not associated with the KBI module.
9.4.2
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs in a KBI
module must be at the deasserted logic level.
A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level)
during one bus cycle and then a logic 0 (the asserted level) during the next cycle.
A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1
during the next cycle.
The KBIMOD control bit can be set to reconfigure the detection logic so that it detects edges and levels.
In KBIMOD = 1 mode, the KBF status flag becomes set when an edge is detected (when one or more
enabled pins change from the deasserted to the asserted level while all other enabled pins remain at their
deasserted levels), but the flag is continuously set (and cannot be cleared) as long as any enabled keyboard
input pin remains at the asserted level. When the MCU enters stop mode, the synchronous edge-detection
logic is bypassed (because clocks are stopped). In stop mode, KBI inputs act as asynchronous
level-sensitive inputs so they can wake the MCU from stop mode.
Freescale Semiconductor
KBIPE[7:0]
Reset
Field
7:0
W
R
Functional Description
KBIPE7
KBI Pin Enable Register (KBI1PE)
Pin Enables
Edge and Level Sensitivity
Keyboard Pin Enable for KBI Port Bits — Each of these read/write bits selects whether the associated KBI
port pin is enabled as a keyboard interrupt input or functions as a general-purpose I/O pin.
0 Bit n of KBI port is a general-purpose I/O pin not associated with the KBI
1 Bit n of KBI port enabled as a keyboard interrupt input
0
7
= Unimplemented or Reserved
KBIPE6
0
6
Table 9-2. KBI1PE Register Field Descriptions
Figure 9-5. KBI Pin Enable Register (KBI1PE)
KBIPE5
MC9S08GB60A Data Sheet, Rev. 2
0
5
KBIPE4
0
4
Description
KBIPE3
3
0
KBIPE2
0
2
Keyboard Interrupt (S08KBIV1)
KBIPE1
0
1
KBIPE0
0
0
153