MC9S08GB60ACFUE Freescale, MC9S08GB60ACFUE Datasheet - Page 144

• Manufacturer Part Number: MC9S08GB60ACFUE
• Manufacturer: Freescale

Specifications of MC9S08GB60ACFUE

• Cpu Family: HCS08
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: I2C/SCI/SPI
• Total Internal Ram Size: 4KB
• # I/os (max): 56
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8/2.08V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 60KB
• Lead Free Status / RoHS Status: Compliant

Chapter 8 Central Processor Unit (S08CPUV2)
144
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
MUL
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
NOP
NSA
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
PSHA
PSHH
PSHX
PULA
PULH
PULX
ROL opr8a
ROLA
ROLX
ROL oprx8,X
ROL ,X
ROL oprx8,SP
Source
Form
Load X (Index Register
Low) from Memory
Logical Shift Left
(Same as ASL)
Logical Shift Right
Move
Unsigned multiply
Negate
(Two’s Complement)
No Operation
Nibble Swap
Accumulator
Inclusive OR Accumulator
and Memory
Push Accumulator onto
Stack
Push H (Index Register
High) onto Stack
Push X (Index Register
Low) onto Stack
Pull Accumulator from
Stack
Pull H (Index Register
High) from Stack
Pull X (Index Register
Low) from Stack
Rotate Left through Carry
Operation
Table 8-2. HCS08 Instruction Set Summary (Sheet 5 of 7)
MC9S08GB60A Data Sheet, Rev. 2
Push (A); SP ← (SP) – 0x0001
Push (H); SP ← (SP) – 0x0001
Push (X); SP ← (SP) – 0x0001
SP ← (SP + 0x0001); Pull (H)
SP ← (SP + 0x0001); Pull (A)
SP ← (SP + 0x0001); Pull (X)
IX+/DIR and DIR/IX+ Modes
0
C
H:X ← (H:X) + 0x0001 in
(M)
M ← – (M) = 0x00 – (M)
M ← – (M) = 0x00 – (M)
M ← – (M) = 0x00 – (M)
M ← – (M) = 0x00 – (M)
X ← – (X) = 0x00 – (X)
A ← – (A) = 0x00 – (A)
C
A ← (A[3:0]:A[7:4])
destination
Uses 1 Bus Cycle
b7
b7
X:A ← (X) × (A)
Description
A ← (A) | (M)
b7
X ← (M)
← (M)
b0
b0
source
b0
C
0
V H I N Z C
0 – –
0 – –
– 0 – – – 0
– – – – – –
– – – – – –
0 – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– – – – – –
– –
– – 0
– –
– –
on CCR
Effect
–
–
–
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR
INH
DIR
INH
INH
IX1
IX
SP1
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
INH
INH
INH
INH
INH
INH
DIR
INH
INH
IX1
IX
SP1
Freescale Semiconductor
9EDE
9EDA
9EEE
9EEA
9E68
9E64
9E60
9E69
AE
BE
CE
DE
EE
AA
BA
CA
DA
EA
FE
9D
FA
4E
5E
6E
7E
8B
8A
38
48
58
68
78
34
44
54
64
74
42
30
40
50
60
70
62
87
89
86
88
39
49
59
69
79
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
dd
ff
ff
dd dd
dd
ii dd
dd
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
2
3
4
4
3
3
5
4
5
1
1
5
4
6
5
1
1
5
4
6
5
5
4
5
5
5
1
1
5
4
6
1
1
2
3
4
4
3
3
5
4
2
2
2
3
3
3
5
1
1
5
4
6